Storage device and method of operating storage device
A storage device includes at least one nonvolatile memory device, a volatile memory device and a storage controller. The storage controller performs an error correction code (ECC) decoding on a read data read from the volatile memory device, in response to uncorrectable errors being detected in the read data, corrects the uncorrectable errors that are not correctable by the ECC decoding to generate corrected data by performing an erasure decoding on the read data, replaces a defective word-line of a first memory region with a redundancy word-line of a second memory region by performing a soft post package repair PPR on the first memory region that stores the read data, stores the corrected data in the second memory region and performs a re-read operation on the second memory region.
1 . A storage device comprising:
at least one nonvolatile memory device;
a volatile memory device; and
a storage controller configured to control the at least one nonvolatile memory device and the volatile memory device,
wherein the storage controller is configured to:
perform an error correction code (ECC) decoding on a read data that is read from the volatile memory device;
based on errors that are uncorrectable by the ECC decoding being detected in the read data, correct the errors to generate corrected data by performing an erasure decoding on the read data, wherein performing the erasure decoding comprises:
writing, as a written data pattern, a data pattern in a first memory region in which the errors are detected;
reading, as a read data pattern, the data pattern from the first memory region; and
determining at least one erasure location in the read data based on comparing the written data pattern and the read data pattern;
replace a defective word-line of the first memory region with a redundancy word-line of a second memory region by performing a soft post package repair (PPR) on the first memory region that stores the read data;
store the corrected data in the second memory region; and
perform a re-read operation on the second memory region.
2 . The storage device of claim 1 , wherein the storage controller includes:
a central processing unit (CPU) configured to control operation of the storage controller;
a memory controller configured to perform an access operation on the volatile memory device;
an ECC decoder configured to:
receive the read data from the memory controller,
perform the ECC decoding on the read data, and
activate an error flag signal based on the errors being detected in the read data;
an uncorrectable error (UE) data buffer configured to store the read data in which the errors are detected; and
an erasure decoder configured to perform the erasure decoding on the read data stored in the UE data buffer.
3 . The storage device of claim 2 , wherein:
the memory controller is configured to provide an interrupt signal to the CPU based on receiving the activated error flag signal from the ECC decoder; and
the CPU is configured to enter the erasure decoder and the memory controller into a recovery process.
4 . The storage device of claim 3 ,
wherein the memory controller is configured to, in the recovery process,
write the data pattern in the first memory region as the written data pattern;
read the data pattern from the first memory region as the read data pattern; and
provide the written data pattern and the read data pattern to the erasure decoder, and
wherein the erasure decoder is configured to, in the recovery process, perform the erasure decoding by:
determining the at least one erasure location in the read data stored in the UE data buffer;
estimating an error magnitude based on error positions in at least one target symbol corresponding to the at least one erasure location; and
correcting errors of the target symbol based on the estimated error magnitude.
5 . The storage device of claim 4 , wherein the erasure decoder is configured to determine the at least one erasure location by comparing the written data pattern and the read data pattern by unit of a symbol.
6 . The storage device of claim 4 , wherein the erasure decoder is configured to generate a corrected data by correcting error bits of the at least one target symbol corresponding to the at least one erasure location, in the read data stored in the UE data buffer.
7 . The storage device of claim 4 , wherein the erasure decoder is configured to:
generate a corrected data by correcting error bits of the at least one target symbol corresponding to the at least one erasure location, in the read data stored in the UE data buffer; and
provide the memory controller with a result of the erasure decoding and the corrected data.
8 . The storage device of claim 7 , wherein the memory controller is configured to:
control the volatile memory device to perform the soft PPR, based on the result of the erasure decoding; and
provide an interrupt termination signal to the CPU based on the soft PPR being completed.
9 . The storage device of claim 7 , wherein:
the CPU is configured to apply a command designating the re-read operation to the memory controller based on the interrupt signal; and
the memory controller is configured to:
read the corrected data from the second memory region based on the command; and
provide the CPU with the corrected data read from the second memory region.
10 . The storage device of claim 1 , wherein the storage controller is configured to store information associated with the soft PPR in the at least one nonvolatile memory device.
11 . The storage device of claim 10 , wherein the at least one nonvolatile memory device is configured to provide the volatile memory device with the information associated with the soft PPR after a power of the storage device is reset.
12 . The storage device of claim 10 , wherein the information associated with the soft PPR includes information on a defective address of the defective word-line of the first memory region and a replacement address of the redundancy word-line of the second memory region.
13 . The storage device of claim 1 , wherein the volatile memory device includes:
a memory cell array including a plurality of bank arrays, each of the plurality of bank arrays including a plurality of volatile memory cells coupled to a plurality of word-lines and a plurality of bit-lines;
a row decoder coupled to the memory cell array through the plurality of word-lines;
a control logic circuit configured to control access on the memory cell array based on a command and an address from the memory controller; and
a repair controller configured to perform the soft PPR based on information associated with the soft PPR.
14 . The storage device of claim 1 ,
wherein information associated with the soft PPR includes information on a defective address of the defective word-line of the first memory region and a replacement address of the redundancy word-line of the second memory region, and
wherein the repair controller is configured to:
store the information associated with the soft PPR therein; and
based on an access address from the memory controller matching the defective address, provide a row decoder with the replacement address that replaces the defective address.
15 . The storage device of claim 14 , wherein the at least one nonvolatile memory device is configured to provide the repair controller with the information associated with the soft PPR after a power of the storage device is reset.
16 . The storage device of claim 1 , wherein:
the storage controller is connected to an external host through a compute express link (CXL) interface and is configured to process a request from the external host; and
the nonvolatile memory device is configured to operate as a buffer memory configured to store data associated with an operation of the nonvolatile memory device.
17 . A method of operating a storage device, comprising:
performing an error correction code (ECC) decoding on a read data that is read from a volatile memory device;
based on errors that are uncorrectable by the ECC decoding being detected in the read data, correcting the errors to generate corrected data by performing an erasure decoding on the read data, wherein performing the erasure decoding comprises:
writing, as a written data pattern, a data pattern in a first memory region in which the errors are detected;
reading, as a read data pattern, the data pattern from the first memory region; and
determining at least one erasure location in the read data based on comparing the written data pattern and the read data pattern; and
replacing, by the volatile memory device, a defective word-line of the first memory region with a redundancy word-line of a second memory region by performing a soft post package repair (PPR) on the first memory region that stores the read data.
18 . The method of claim 17 , further comprising:
copying data stored in the first memory region to a second memory region in the volatile memory device;
writing the corrected data in the second memory region; and
performing a re-read operation on the second memory region.
19 . The method of claim 17 , further comprising:
storing information associated with the soft PPR in at least one nonvolatile memory device, and
wherein performing the erasure decoding includes:
correcting error bits of at least one target symbol corresponding to the at least one erasure location, in the read data.
20 . A storage device comprising:
at least one nonvolatile memory device;
a volatile memory device; and
a storage controller configured to control the at least one nonvolatile memory device and the volatile memory device,
wherein the storage controller includes:
a memory controller configured to perform an access operation on the volatile memory device,
an error correction code (ECC) decoder configured to:
receive read data from the memory controller,
perform the ECC decoding on the read data, and
activate an error flag signal based on errors that are uncorrectable by the ECC decoding being detected in the read data,
an uncorrectable error (UE) data buffer configured to store the read data in which the errors are detected, and
an erasure decoder configured to correct the errors to generate corrected data by performing an erasure decoding on the read data stored in the UE data buffer,
wherein performing the erasure decoding comprises:
writing, as a written data pattern, a data pattern in a first memory region in which the errors are detected;
reading, as a read data pattern, the data pattern from the first memory region; and
determining at least one erasure location in the read data based on comparing the written data pattern and the read data pattern,
and wherein the memory controller is configured to:
replace a defective word-line of the first memory region with a redundancy word-line of a second memory region by performing a soft post package repair on the first memory region that stores the read data in the volatile memory device, based on a result of the erasure decoding,
store the corrected data in the second memory region, and
perform a re-read operation on the second memory region.