Semiconductor device and method for making the same
The present disclosure relates to a hybrid integrated circuit. In one implementation, an integrated circuit may have a first region with a first gate structure having a ferroelectric gate dielectric, at least one source associated with the first gate of the first region, and at least one drain associated with the first gate structure of the first region. Moreover, the integrated circuit may have a second region with a second gate structure having a high-κ gate dielectric, at least one source associated with the second gate structure of the second region, and at least one drain associated with the second gate structure of the second region. The integrated circuit may further have at least one trench isolation between the first region and the second region.
1 . An integrated circuit, comprising:
a first region comprising at least one first gate structure having a ferroelectric gate dielectric and being associated with a first source and a first drain;
a second region adjacent to the first region, the second region comprising at least one second gate structure having a high-κ gate dielectric, and being associated with a second source and a second drain; and
a first trench isolation in contact with a drain of the first region and a source of the second region, wherein a width of the first trench isolation is selected to avoid hysteresis of the at least one first gate structure during activation of the at least one second gate structure.
2 . The integrated circuit of claim 1 , wherein the ferroelectric gate dielectric has a thickness between about 0.5 nm and about 20 nm.
3 . The integrated circuit of claim 1 , wherein a ratio between an area of the first region having the at least one first gate structure to an area of the second region having the at least one second gate structure is 3:1.
4 . The integrated circuit of claim 1 , further comprising:
a third region adjacent to the first region, the second region and the third region being on opposite sides of the first region, the third region comprising at least one third gate structure having the high-κ gate dielectric; and
a second trench isolation between the first region and the third region, the second trench isolation being in contact with a source of the first region and a drain of the third region.
5 . The integrated circuit of claim 1 , wherein the first gate structure comprises an interfacial layer, a ferroelectric film, and a metal layer.
6 . The integrated circuit of claim 5 , wherein the metal layer comprises at least one of Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TSN, TaN, Ru, Mo, Al, WN, Cu, or W.
7 . The integrated circuit of claim 5 , wherein the ferroelectric film comprises one of perovskites, HfO2-based compounds, or organic polymers.
8 . The integrated circuit of claim 7 , wherein the ferroelectric film comprises at least one of Pb(Zr, Ti)O3, SrBi2Ta2O9, BaTiO3, (Bi, La)4Ti3O12, HfZrO, HfGeO, HfLaO, HfNO, HfSiO, HfGdO, HfYO, HfScO, HfNbO, HfAlO, PolyVinylidene Fluoride, or TrFE (Trifluoroethylene).
9 . The integrated circuit of claim 1 , wherein the second gate structure comprises an interfacial layer, a dielectric film, and a metal layer.
10 . The integrated circuit of claim 9 , wherein the dielectric film comprises at least one of HfO2, LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba, Sr)TiO3 (BST), Al2O3, Si3N4, or a silicon oxynitride (SiOxNy).
11 . The integrated circuit of claim 9 , wherein the metal layer comprises at least one of Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TSN, TaN, Ru, Mo, Al, WN, Cu, or W.
12 . A method of fabricating an integrated circuit, comprising:
forming one or more source regions and one or more drain regions on a substrate;
forming an interfacial layer over the one or more source regions and the one or more drain regions;
forming a ferroelectric film and a dielectric film over respective portions of the interfacial layer;
forming metal over the ferroelectric film and the dielectric film; and
etching portions of the interfacial layer, the ferroelectric film, the dielectric film, and the metal over the one or more source regions and the one or more drain regions, to form an integrated circuit comprising a first region, a second region adjacent to the first region, and a first trench isolation contacting a drain of the first region and a source of the second region.
13 . The method of claim 12 , further comprising:
forming a sacrificial layer over the interfacial layer before forming the ferroelectric film or forming the dielectric film.
14 . The method of claim 13 , further comprising:
forming a protective layer on the sacrificial layer over portions corresponding to the ferroelectric film; and
etching the sacrificial layer before forming the dielectric film.
15 . The method of claim 13 , further comprising:
forming a protective layer on the sacrificial layer over portions corresponding to the dielectric film; and
etching the sacrificial layer before forming the ferroelectric film.
16 . The method of claim 12 , further comprising:
forming a protective layer on the dielectric film;
etching the dielectric film; and
etching the protective layer before forming the metal.
17 . The method of claim 12 , further comprising:
forming a protective layer on the ferroelectric film;
etching the ferroelectric film; and
etching the protective layer before forming the metal.
18 . The method of claim 12 , further comprising:
forming a protective layer over the metal; and
etching the protective layer after etching portions of the interfacial layer, the ferroelectric film, the dielectric film, and the metal.
19 . The method of claim 12 , further comprising:
forming isolation trenches between the portions corresponding to the ferroelectric film and the portions corresponding to the dielectric film.
20 . A semiconductor device, comprising:
a first region comprising one or more first gate structures having a ferroelectric gate dielectric material and is configured for activation using direct current;
a second region comprising one or more second gate structures having a high-κ gate dielectric material and is configured for activation using alternating current; and
one or more isolation regions comprising at least one trench isolation contacting a drain of the first region and a source of the second region, wherein a width of the at least one trench isolation is selected to avoid hysteresis of the one or more first gate structures during activation of the one or more second gate structures;
wherein the first region and the second region are wired for separate activations and the one or more first gate structures and the one or more second gate structures are coplanar on one or more planes perpendicular to a direction of the at least one trench isolation.