Display having semiconducting oxide gate driver circuitry with bottom gate terminals for reduced leakage
A driver circuit configured to output a control signal to a row of display pixels is provided. The driver circuit can include a first transistor having a drain terminal coupled to a first positive power supply line, a gate terminal, and a source terminal that is coupled to an output port of the driver circuit on which the control signal is generated and a second transistor having a drain terminal coupled to the output port of the driver circuit, a gate terminal, and a source terminal that is coupled to a first ground power supply line. The first and second transistors can be coupled to a plurality of transistors coupled between a second positive power supply line and a second ground power supply line, configured to receive one or more clocks signals, and at least some of which include bottom gate terminals.
1 . A driver circuit configured to output a control signal to a row of display pixels, comprising:
a first transistor having a drain terminal coupled to a first positive power supply line, a gate terminal, and a source terminal that is coupled to an output port of the driver circuit, the control signal being generated at the output port;
a second transistor having a drain terminal coupled to the output port of the driver circuit, a gate terminal, and a source terminal that is coupled to a first ground power supply line;
a third transistor having a drain terminal coupled to a second positive power supply line different than the first positive power supply line, a gate terminal coupled to the gate terminal of the first transistor, a source terminal on which a carry output signal is generated, and a bottom gate terminal shorted to its source terminal;
a fourth transistor having a drain terminal coupled to the source terminal of the third transistor, a gate terminal coupled to the gate terminal of the second transistor, and a source terminal coupled to a second ground power supply line different than the first ground power supply line; and
a fifth transistor having a gate terminal coupled to the gate terminal of the first transistor, a drain terminal coupled to the gate terminal of the second transistor, a source terminal coupled to the second ground power supply line, and a bottom gate terminal coupled to the second ground power supply line.
2 . The driver circuit of claim 1 , further comprising:
a capacitor having a first terminal coupled to the gate terminal of the first transistor and having a second terminal coupled to the output port of the driver circuit.
3 . The driver circuit of claim 1 , further comprising:
a sixth transistor having a first source-drain terminal configured to receive a carry output signal from an additional driver circuit, a gate terminal configured to receive a clock signal, and a second source-drain terminal coupled to a first node;
a seventh transistor having a first source-drain terminal coupled to the first node, a gate terminal configured to receive the clock signal, and a second source-drain terminal coupled to the gate terminal of the first transistor; and
an eighth transistor having a drain terminal coupled to the second positive power supply line, a gate terminal coupled to the gate terminal of the first transistor, a source terminal coupled to the first node, and a bottom gate terminal shorted to its source terminal.
4 . The driver circuit of claim 3 , further comprising:
a ninth transistor having a drain terminal coupled to the second positive power supply line, a gate terminal coupled to the second positive power supply line, a source terminal, and a bottom gate terminal coupled to the second ground power supply line;
a tenth transistor having a drain terminal coupled to the source terminal of the ninth transistor, a gate terminal coupled to the second positive power supply line, and a source terminal coupled to a second node;
an eleventh transistor having a drain terminal coupled to the second positive power supply line, a gate terminal configured to receive the clock signal, and a source terminal;
a twelfth transistor having a drain terminal coupled to the source terminal of the eleventh transistor, a gate terminal coupled to the second node, and a source terminal coupled to the gate terminal of the second transistor;
a capacitor coupled across the gate and source terminals of the twelfth transistor; and
a thirteenth transistor having a drain terminal coupled to the second node, a gate terminal coupled to the first node, a source terminal coupled to the second ground power supply line, and a bottom gate terminal coupled to the second ground power supply line.
5 . The driver circuit of claim 4 , further comprising:
a first discharge transistor having a drain terminal coupled to the second node, a source terminal coupled to the second ground power supply line, a gate terminal configured to receive a clear signal, and a bottom gate terminal coupled to the second ground power supply line;
a second discharge transistor having a drain terminal coupled to the gate terminal of the first transistor, a source terminal coupled to the second ground power supply line, a gate terminal configured to receive the clear signal, and a bottom gate terminal coupled to the second ground power supply line;
a third discharge transistor having a drain terminal coupled to the gate terminal of the second transistor, a source terminal coupled to the second ground power supply line, a gate terminal configured to receive the clear signal, and a bottom gate terminal coupled to the second ground power supply line; and
a fourth discharge transistor having a drain terminal coupled to the output port of the driver circuit, a source terminal coupled to the first ground power supply line, a gate terminal configured to receive the clear signal, and a bottom gate terminal coupled to the first ground power supply line.
6 . A driver circuit configured to output a control signal to a row of display pixels, comprising:
a first transistor having a drain terminal coupled to a first positive power supply line, a gate terminal, and a source terminal that is coupled to an output port of the driver circuit, wherein the control signal is configured to be produced at the output port;
a second transistor having a drain terminal coupled to the output port of the driver circuit, a gate terminal, and a source terminal that is coupled to a first ground power supply line;
a third transistor having a drain terminal coupled to the gate terminal of the second transistor, a gate terminal coupled to the gate terminal of the first transistor, a source terminal coupled to a second ground power supply line different than the first ground power supply line, and a bottom gate terminal shorted to its source terminal;
a fourth transistor having a drain terminal coupled to the drain terminal of the third transistor, a source terminal coupled to the second ground power supply line, a gate terminal, and a bottom gate terminal shorted to its source terminal; and
a first additional transistor having a gate terminal configured to receive a clock signal and a source-drain terminal coupled to the gate terminal of the fourth transistor.
7 . The driver circuit of claim 6 , further comprising:
a second additional transistor having a drain terminal coupled to a second positive power supply line different than the first positive power supply line, a gate terminal coupled to the gate terminal of the first transistor, a source terminal on which a carry output signal is generated, and a bottom gate terminal shorted to its source terminal.
8 . The driver circuit of claim 6 , further comprising:
a fifth transistor having a drain terminal coupled to a second positive power supply line different than the first positive power supply line, a gate terminal configured to receive the clock signal, and a source terminal;
a sixth transistor having a drain terminal coupled to the source terminal of the fifth transistor, a source terminal coupled to the gate terminal of the second transistor, and a gate terminal coupled to the drain terminal of the fourth transistor; and
a capacitor having a first terminal coupled to the drain terminal of the fourth transistor and having a second terminal coupled to the source terminal of the sixth transistor.
9 . The driver circuit of claim 6 , further comprising:
a fifth transistor having a drain terminal coupled to a second positive power supply line different than the first positive power supply line, a gate terminal coupled to the second positive power supply line, a source terminal, and a bottom terminal coupled to the second ground power supply line; and
a sixth transistor having a drain terminal coupled to the source terminal of the source terminal of the fifth transistor, a gate terminal shorted to the gate terminal of the fifth transistor, and a source terminal coupled to the drain terminal of the fourth transistor.
10 . The driver circuit of claim 6 , further comprising:
a first discharge transistor having a drain terminal coupled to the output port of the driver circuit, a source terminal coupled to the first ground power supply line, a gate terminal configured to receive a clear signal, and a bottom gate terminal coupled to the first ground power supply line.
11 . The driver circuit of claim 10 , further comprising:
a second discharge transistor having a drain terminal coupled to the gate terminal of the second transistor, a source terminal coupled to the second ground power supply line, a gate terminal configured to receive the clear signal, and a bottom gate terminal coupled to the second ground power supply line.
12 . A driver circuit configured to output a control signal to a row of display pixels, comprising:
a first transistor having a drain terminal coupled to a first positive power supply line, a gate terminal, and a source terminal that is coupled to an output port of the driver circuit, wherein the control signal is configured to be produced at the output port;
a second transistor having a drain terminal coupled to the output port of the driver circuit, a gate terminal, and a source terminal that is coupled to a first ground power supply line;
a first discharge transistor having a drain terminal coupled to the output port of the driver circuit, a source terminal coupled to the first ground power supply line, a gate terminal configured to receive a clear signal, and a bottom gate terminal coupled to the first ground power supply line;
a capacitor having a first terminal coupled to the gate terminal of the second transistor and having a second terminal; and
a second discharge transistor having a drain terminal coupled to the second terminal of the capacitor, a source terminal coupled to a second ground power supply line, a gate terminal configured to receive the clear signal, and a bottom gate terminal coupled to the second ground power supply line.
13 . The driver circuit of claim 12 , further comprising:
an additional transistor having a drain terminal coupled to a second positive power supply line different than the first positive power supply line, a gate terminal coupled to the gate terminal of the first transistor, a source terminal on which a carry output signal is generated, and a bottom gate terminal shorted to its source terminal.
14 . The driver circuit of claim 12 , further comprising:
a third discharge transistor having a drain terminal coupled to the gate terminal of the second transistor, a source terminal coupled to the second ground power supply line, a gate terminal configured to receive the clear signal, and a bottom gate terminal coupled to the second ground power supply line.
15 . The driver circuit of claim 14 , further comprising:
a fourth discharge transistor having a drain terminal coupled to the gate terminal of the first transistor, a source terminal coupled to the second ground power supply line, a gate terminal configured to receive the clear signal, and a bottom gate terminal coupled to the second ground power supply line.
16 . The driver circuit of claim 15 , further comprising:
an additional transistor having a drain terminal coupled to a second positive power supply line different than the first positive power supply line, a gate terminal coupled to the gate terminal of the first transistor, a source terminal, and a bottom gate terminal shorted to its source terminal.