Multi-chip synchronization for digital radars
A multi-chip MIMO radar system includes a plurality of transmitters and a plurality of receivers. Each of the pluralities of transmitters and receivers are arranged across a plurality of chips. The multi-chip MIMO radar system is configured to provide an exemplary chip synchronization such that the transmitters and receivers of each chip of the radar system are synchronized with the transmitters and receivers of every other chip of the radar system.
1. A multi-chip MIMO radar system comprising a plurality of chips, the MIMO radar system comprising:
a first integrated circuit chip (chip) of the plurality of chips comprising a first plurality of transmitters and a first plurality of receivers; and
a second chip of the plurality of chips comprising a second plurality of transmitters and a second plurality of receivers;
wherein the second chip is configured to align an own internal timing clock value of the second chip with respect to a reference clock signal, such that the first pluralities of transmitters and receivers are respectively synchronized with the second pluralities of transmitters and receivers, and wherein the second chip of the plurality of chips is configured to perform an intra synchronization of the second plurality of transmitters and the second plurality of receivers comprising selected delays of the own internal timing clock value to account for respective different propagation delays among the second plurality of transmitters and the second plurality of receivers.
2. The multi-chip MIMO radar system of claim 1 , wherein the first chip is configured to align an own internal timing clock value of the first chip with respect to the reference clock signal.
3. The multi-chip MIMO radar system of claim 2 , wherein the first chip is configured to define the reference clock signal.
4. The multi-chip MIMO radar system of claim 1 , wherein the second chip is configured to delay the reference clock signal at the second chip to account for propagation delays of the reference clock signal.
5. The multi-chip MIMO radar system of claim 4 , wherein the second chip is configured to delay the reference clock signal by a selected multiple of a sub-value of the reference clock signal.
6. The multi-chip MIMO radar system of claim 1 , wherein each chip of the plurality of chips is configured to perform an intra synchronization such that all transmitters and receivers of each chip are synchronized, and wherein each respective intra synchronization comprises selected delays of respective internal timing clock values to account for respective different propagation delays among the transmitters and receivers of each respective chip of the plurality of chips.
7. The multi-chip MIMO radar system of claim 6 , wherein each chip of the plurality of chips comprises a local clock operable to generate a common clock signal, wherein each chip is configured to divide a respective common clock signal such that each transmitter and receiver of each respective chip receives a respective sample clock signal derived from the respective common clock signal, and wherein each chip is configured to synchronize respective transmitter clock dividers and receiver clock dividers to transition on a same edge as their respective common clock signals.
8. The multi-chip MIMO radar system of claim 6 , wherein each chip is configured to individually delay clock signal values by selected multiples of a sub-clock value to account for the different transmitter/receiver routing on the respective chips.
9. The multi-chip MIMO radar system of claim 1 , wherein the first chip comprises a reference clock configured to transmit the reference clock signal that is received by the first and second chips, and wherein the second chip is configured to synchronize with the first chip with respect to the reference clock signal received by the first and second chips.
10. The multi-chip MIMO radar system of claim 1 , wherein a first portion of the plurality of chips is configured to perform a first portion of post processing of received data, and wherein a second portion of the plurality of chips is configured to perform a second portion of the post processing of the received data.
11. A method for synchronizing the chips of a multi-chip MIMO radar system, the method comprising:
powering up each chip of a plurality of chips and starting local clocks of each chip;
intra synchronizing transmitters and receivers of each chip of the plurality of chips;
performing a first synchronization of the plurality of chips with respect to a reference clock signal received by each of the plurality of chips; and
performing a second synchronization of the plurality of chips to synchronize transmitters and receivers of a second chip of the plurality of chips to transmitters and receivers of a first chip of the plurality of chips;
wherein performing the second synchronization of the plurality of chips comprises adjusting a clock signal of the second chip such that an offset between the first chip and the second chip is below a threshold value; and
wherein adjusting a clock signal of the second chip comprises delaying the reference clock signal at the second chip by selected respective multiples of a sub-value of the reference clock signal to account for each respective propagation delay of the reference clock signal among a second plurality of transmitters and a second plurality of receivers of the second chip.
12. The method of claim 11 , wherein the second synchronization comprises:
transmitting, with the first chip, a scan of a selected duration comprising a selected quantity of codes of a selected pattern, wherein the duration of the transmitted scan is one pulse repetition interval;
receiving, with the plurality of chips, the radio signal that is the transmitted scan;
correlating, with the plurality of chips, the received radio signal; and
using the correlation output of the second chip to determine the offset between the second chip and the first chip.
13. The method of claim 12 , wherein each chip of the plurality of chips comprises a local clock signal that is divided such that each transmitter and receiver of each respective chip receives a respective sample clock that is derived from their respective common clock signals, and wherein intra synchronizing the transmitters and receivers of each chip comprises initiating a START signal on each chip that synchronizes all respective transmitter dividers and all receiver dividers to transition on a respective same edge of their respective clock signals, such that the transmitters and receivers of each respective chip are synchronized.
14. The method of claim 13 , wherein each chip individually delays each of their respective clock signal values by selected multiples of a sub-clock value to account for different transmitter/receiver routing on the respective chips.
15. The method of claim 11 , wherein performing the first synchronization of the plurality of chips comprises transmitting, with a reference clock of the first chip, the reference clock signal, wherein the reference clock signal is used to synchronize timers of each chip of the plurality of chips to a timer of the first chip.
16. The method of claim 11 , wherein performing the first synchronization of the plurality of chips comprising transmitting, with a reference clock of the radar system, the reference clock signal, wherein the reference clock signal is used to synchronize timers of each chip of the plurality of chips to a timer of the first chip.
17. The method of claim 11 , wherein the first synchronization of the plurality of chips synchronizes the plurality of chips to within 10-100 ns.
18. The method of claim 11 , wherein the second synchronization of the plurality of chips comprises the use of inter-range bin interpolation to compute a sub-chip misalignment between the first chip and every other chip of the plurality of chips, and wherein correcting the misalignment comprises removing a selected number of clock pulses such that subsequent scans are aligned to the desired degree of synchronization.
19. The method of claim 11 , wherein a first portion of the plurality of chips performs a first portion of post processing of received data, and wherein a second portion of the plurality of chips performs a second portion of the post processing of the received data.