IP Library Granted Patent US 12,603,609
Granted Patent B2
US 12,603,609 · App. 18/656,370 · Granted Apr 14, 2026

Quadrature oscillator

Inventors: Florence Giry-Cassan (Corenc, FR); Antoine Ranieri (Montbonnot-Saint-Martin, FR)
Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
H03B5/1228H03B5/1212H03B2200/0078
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Quick Facts
Patent No.
US 12,603,609
App. No.
18/656,370
Granted
Apr 14, 2026
Kind
B2
Abstract

The present description concerns a device comprising two oscillators coupled to each other so as to operate in quadrature, each oscillator comprising an inductor and a capacitive element having a value selectable from among at least two values, each corresponding to an operating frequency value of the oscillators, each oscillator being configured so that, for each operating frequency value of the oscillators, the quality factor of its inductor is lower than the quality factor of its capacitive element.

Claims (54)

1 . A device comprising:

two oscillators coupled to each other, the two oscillators being configured to operate in quadrature, each oscillator comprising an inductor and a capacitor, the capacitor comprising a value selectable from among at least two values, each corresponding to an operating frequency value of the oscillators, each oscillator being configured so that, for each operating frequency value of the oscillators, the quality factor of its inductor is lower than the quality factor of its capacitor, wherein, in each oscillator, the inductor comprises:

identical first and second windings, the first winding having a first end coupled to a first node of application of a power supply potential and a second end coupled to a second output node of the oscillator, and the second winding having a first end coupled to the first node and a second end coupled to a third output node of the oscillator, a first electrode of the capacitor being connected to the second output node and a second electrode of the capacitor being connected to the third output node; and

a first resistor series-connected to the first winding between the first node and the second output node and a second resistor series-connected to the second winding between the first node and the third output node, the first and second resistors having a same resistance value, each of the first and second resistors comprising:

at least one polysilicon portion;

a first conductive portion of a first metal level of an interconnection structure, the first conductive portion corresponding to a first terminal of the respective resistor;

a second conductive portion of the first metal level corresponding to a second terminal of the respective resistor;

at least one third conductive portion of a second metal level of the interconnection structure;

at least one fourth conductive portion of the second metal level;

first conductive vias electrically coupling the first conductive portion to the at least one third conductive portion and the second conductive portion to the at least one fourth conductive portion; and

second conductive vias electrically coupling the at least one polysilicon portion to the at least one third conductive portion and to the at least one fourth conductive portion.

2 . The device according to claim 1 , wherein each of the first and second resistors has a resistance value in a range from 0.5 to 5 ohms, the capacitance of the capacitor being in a range from 0.5 to 2.0 pF, and the inductance of the inductor having a value in a range from 300 to 700 pH.

3 . The device according to claim 1 , wherein, in each of the oscillators, the capacitor comprises a plurality of switch capacitors coupled with switches configured so that each of the at least two values corresponds to a given combination of off and on states of the switches.

4 . The device according to claim 3 , wherein, in each of the oscillators, the capacitor with a selectable value further comprises varicap diodes.

5 . The device according to claim 1 , wherein each operating frequency value belongs to a range from 5 GHz to 10 GHz.

6 . The device according to claim 1 , wherein the operating frequency values comprise a first value in a range from 5 to 6.5 GHz and a second value in a range from 8.5 to 10 GHz.

7 . The device according to claim 1 , wherein each of the operating frequency values is separated from the other operating frequency values by at least 0.5 GHz.

8 . A device comprising:

two oscillators coupled to each other, the two oscillators being configured to operate in quadrature, each oscillator comprising an inductor and a capacitor, each respective inductor comprising respective first and second windings and a respective resistor, the respective first winding having a respective first end coupled to a respective first node of application of a power supply potential and a respective second end coupled to a respective second output node of the oscillator, the respective second winding having a respective first end coupled to the respective first node and a respective second end coupled to a respective third output node of the oscillator, a respective first electrode of the respective capacitor being connected to the respective second output node and a respective second electrode of the respective capacitor being connected to the respective third output node, and each oscillator being configured so that, for each operating frequency value of the oscillators, the quality factor of its respective inductor is lower than the quality factor of its respective capacitor, the respective resistor being series-connected to the first winding between the respective first node and the respective second output node, the respective resistor comprising:

at least one polysilicon portion;

a first conductive portion of a first metal level of an interconnection structure, the first conductive portion corresponding to a first terminal of the respective resistor;

a second conductive portion of the first metal level corresponding to a second terminal of the respective resistor;

at least one third conductive portion of a second metal level of the interconnection structure;

at least one fourth conductive portion of the second metal level;

first conductive vias electrically coupling the first conductive portion to the at least one third conductive portion and the second conductive portion to the at least one fourth conductive portion; and

second conductive vias electrically coupling the at least one polysilicon portion to the at least one third conductive portion and to the at least one fourth conductive portion.

9 . The device according to claim 8 , wherein each of the oscillators further comprises:

a first MOS transistor and a second MOS transistor each having a first conduction terminal connected to the second output node and a second conduction terminal coupled to a fifth node of application of a reference potential, the first MOS transistor having its gate coupled to the third output node; and

a third MOS transistor and a fourth MOS transistor each having a first conduction terminal connected to the third output node and a second conduction terminal coupled to the fifth node, the third MOS transistor having its gate coupled to the second output node.

10 . The device according to claim 9 , wherein:

the second MOS transistor of a first oscillator of the two oscillators has its gate coupled to the second output node of a second oscillator of the two oscillators;

the fourth MOS transistor of the first oscillator has its gate coupled to the third output node of the second oscillator;

the second MOS transistor of the second oscillator has its gate coupled to the third output node of the first oscillator; and

the fourth MOS transistor of the second oscillator has its gate coupled to the second output node of the first oscillator.

11 . The device according to claim 9 , wherein each of the oscillators comprises:

a first current source having a first terminal connected to the second conduction terminals of the first and third MOS transistors of the oscillator, and a second terminal connected to the fifth node; and

a second current source having a first terminal connected to the second conduction terminals of the second and fourth MOS transistors of the oscillator, and a second terminal connected to the fifth node.

12 . A device comprising:

two oscillators coupled to each other, the two oscillators being configured to operate in quadrature, each oscillator comprising an inductor and a capacitor, each oscillator being configured so that, for each operating frequency value of the oscillators, the quality factor of its inductor is lower than the quality factor of its capacitor, the inductor comprising at least one resistor, the resistor comprising:

a portion of non-doped polysilicon on a semiconductor substrate;

a first conductive portion of a first metal level of an interconnection structure, the first conductive portion corresponding to a first terminal of the resistor;

a second conductive portion of the first metal level corresponding to a second terminal of the resistor;

at least one third conductive portion of a second metal level of the interconnection structure;

at least one fourth conductive portion of the second metal level;

first conductive vias electrically coupling the first conductive portion to the at least one third conductive portion and the second conductive portion to the at least one fourth conductive portion; and

second conductive vias electrically coupling the portion of non-doped polysilicon to the at least one third conductive portion and to the at least one fourth conductive portion.

13 . The device according to claim 12 , wherein, in each of the oscillators, the capacitor further comprises varicap diodes.

14 . The device according to claim 12 , wherein each operating frequency value belongs to a range from 5 GHz to 10 GHz.

15 . The device according to claim 12 , wherein the operating frequency values comprise a first value in a range from 5 to 6.5 GHz and a second value in a range from 8.5 to 10 GHz.

16 . The device according to claim 12 , wherein each of the operating frequency values is separated from the other operating frequency values by at least 0.5 GHz.

17 . The device according to claim 1 , wherein each of the resistors comprises two respective polysilicon portions.

18 . The device according to claim 1 , wherein the at least one polysilicon portion directly rests on a semiconductor substrate.

19 . The device according to claim 1 , wherein the at least one polysilicon portion is separated from a semiconductor substrate by an insulating layer between the at least one polysilicon portion and the semiconductor substrate.

20 . The device according to claim 1 , wherein the value is selectable from among five frequency values respectively equal to 6.4896 GHZ; 7.1136 GHZ; 7.7376 GHz; 8.3616 GHz and 8.9856 GHz.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 30, 2024
From: STMICROELECTRONICS (GRENOBLE 2) SAS
To: STMICROELECTRONICS INTERNATIONAL N.V.
Reel/Frame 068449/0739 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 2, 2024
From: STMICROELECTRONICS FRANCE
To: STMICROELECTRONICS INTERNATIONAL N.V.
Reel/Frame 068165/0513 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 7, 2024
From: GIRY-CASSAN, FLORENCE
To: STMICROELECTRONICS FRANCE
Reel/Frame 067334/0412 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 7, 2024
From: RANIERI, ANTOINE
To: STMICROELECTRONICS (GRENOBLE 2) SAS
Reel/Frame 067334/0442 →
Priority Claims (1)
FR 2304792 · May 15, 2023 · national
Continuity (1)
Related Publication 20240388251A1 · Nov 21, 2024
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