Isolated digital input receiver with sink and source mode support

1 . A circuit, comprising:

a sink/source mode detector having an input terminal and an output terminal, the input terminal of the sink/source mode detector coupled to a first input/output (I/O) terminal of the circuit;

a first logic circuit having an output terminal and having first and second input terminals, the second input terminal of the first logic circuit coupled to the output terminal of the sink/source mode detector;

a second logic circuit having an input terminal and an output terminal, the input terminal of the second logic circuit coupled to the output terminal of the sink/source mode detector;

a third logic circuit having an output terminal and having first and second input terminals, the second input terminal of the third logic circuit coupled to the output terminal of the second logic circuit;

a first switch having a control terminal and first and second terminals, the first terminal of the first switch coupled to a voltage supply terminal, the second terminal of the first switch coupled to the first I/O terminal of the circuit, and the control terminal of the first switch coupled to the output terminal of the third logic circuit; and

a second switch having a control terminal and first and second terminals, the first terminal of the second switch coupled to the first I/O terminal of the circuit, the second terminal of the second switch coupled to a ground terminal, and the control terminal of the second switch coupled to the output terminal of the first logic circuit.

2 . The circuit of claim 1 , further comprising:

a source threshold detector having an input terminal and an output terminal, the input terminal of the source threshold detector coupled to a second I/O terminal of the circuit; and

a sink threshold detector having an input terminal and an output terminal, the input terminal of the sink threshold detector coupled to the second I/O terminal of the circuit.

3 . The circuit of claim 2 , wherein:

the source threshold detector comprises a first comparator having first and second input terminals, the first input terminal of the first comparator coupled to the second I/O terminal of the circuit, and the second input terminal of the first comparator coupled to a first reference signal terminal; and

the sink threshold detector comprises a second comparator having first and second input terminals, the first input terminal of the second comparator coupled to the second I/O terminal of the circuit, and the second input terminal of the second comparator coupled to a second reference signal terminal.

4 . The circuit of claim 3 , further comprising:

a first diode having an anode and a cathode, the anode of the first diode coupled to the second I/O terminal of the circuit;

a first current source having first and second terminals, the first terminal of the first current source coupled to the cathode of the first diode, and the second terminal of the first current source coupled to the first I/O terminal of the circuit;

a second diode having an anode and a cathode, the cathode of the second diode coupled to the second I/O terminal of the circuit; and

a second current source having first and second terminals, the first terminal of the second current source coupled to the anode of the second diode, and the second terminal of the second current source coupled to the first I/O terminal of the circuit.

5 . The circuit of claim 1 , further comprising:

a first light emitting diode (LED) having an anode and a cathode, the anode of the first LED coupled to the first I/O terminal of the circuit, and the cathode of the first LED coupled to a first common terminal of the circuit; and

a second LED having an anode and a cathode, the cathode of the second LED coupled to the first I/O terminal of the circuit and the anode of the second LED coupled to the first common terminal of the circuit.

6 . The circuit of claim 1 , further comprising a resistor having first and second terminals, the first terminal of the resistor coupled to a second common terminal of the circuit.

7 . The circuit of claim 6 , further comprising:

a first diode having an anode and a cathode, the anode of the first diode coupled to the second terminal of the resistor, and the cathode of the first diode coupled to a voltage reference terminal of the circuit;

a second diode having an anode and a cathode, the anode of the second diode coupled to a ground reference terminal of the circuit, and the cathode of the second diode coupled to a first common terminal of the circuit;

a third diode having an anode and a cathode, the cathode of the third diode coupled to the anode of the first diode, and the anode of the third diode coupled to the anode of the second diode; and

a fourth diode having an anode and a cathode, the cathode of the fourth diode coupled to the cathode of the first diode, and the anode of the fourth diode coupled to the cathode of the second diode.

8 . The circuit of claim 1 , wherein the sink/source mode detector comprises a comparator having an output terminal and first and second input terminals, the first input terminal of the comparator coupled to the first I/O terminal of the circuit, the second input terminal coupled to a third reference signal terminal, and in which the output terminal of the comparator is the output terminal of the sink/source mode detector.

9 . The circuit of claim 1 , wherein the first and third logic circuits are each AND logic circuits and the second logic circuit is an inverter.

10 . A circuit, comprising:

a sink/source mode detector having an input terminal and an output terminal, the input terminal of the sink/source mode detector coupled to a first input/output (I/O) terminal of the circuit, the sink/source mode detector configured to:

compare a voltage provided at the first I/O terminal of the circuit to a first reference signal;

determine, responsive to the voltage provided at the first I/O terminal exceeding the first reference signal, that the circuit is in a source mode;

determine, responsive to the voltage provided at the first I/O terminal not exceeding the first reference signal, that the circuit is in a sink mode;

responsive to determining that the circuit is in the source mode and an input signal of the circuit has a value less than a second reference signal, control a first switch to form a first current path between a voltage supply terminal and the first I/O terminal of the circuit; and

responsive to determining that the circuit is in the sink mode and the input signal has a value greater than the second reference signal, control a second switch to form a second current path between a ground terminal and the first I/O terminal of the circuit.

11 . The circuit of claim 10 , wherein:

responsive to determining that the circuit is in the source mode, the sink/source mode detector is configured to control a signal selection circuit to provide a first comparison result as an output signal of the circuit; and

responsive to determining that the circuit is in the sink mode, the sink/source mode detector is configured to control the signal selection circuit to provide a second comparison result as the output signal of the circuit.

12 . The circuit of claim 10 , wherein the sink/source mode detector is configured to compare the voltage provided at the first I/O terminal to the first reference signal having a value equal to one-half of a supply voltage of the circuit.