METHOD FOR READING A MULTI-LEVEL NON-VOLATILE MEMORY DEVICE, IN PARTICULAR A PHASE-CHANGE MEMORY DEVICE, AND MULTI-LEVEL NON-VOLATILE MEMORY DEVICE
A multi-level non-volatile memory cell has N levels, N being even and greater than two, corresponding respectively to N logical data that can be stored in the memory cell and to N corresponding read current ranges. A datum stored in the memory cell is read by performing successive comparisons of a read current output by the memory cell with reference currents selected from a set of N-1 reference currents having values respectively lying between two different successive ranges using a dichotomous algorithm starting with the reference current having the median value.
1 . A method for managing operation of a multi-level non-volatile memory cell, the multi-level non-volatile memory cell having N levels, N being even and greater than two, corresponding respectively to N logical data that can be stored in the multi-level non-volatile memory cell and to N corresponding read current ranges, the method comprising:
reading the datum stored in the multi-level non-volatile memory cell by performing successive comparisons of a read current output by the multi-level non-volatile memory cell with reference currents selected from a set of N-1 reference currents having values respectively lying between two different successive ranges using a dichotomous algorithm starting with the reference current having the median value.
2 . The method according to claim 1 , wherein a reference memory cell that is structurally identical to the multi-level non-volatile memory cell is placed next to the multi-level non-volatile memory cell, and wherein reading comprises successively reading the reference memory cell to cause the reference memory cell to output the corresponding reference currents from the set of N-1 reference currents.
3 . The method according to claim 1 , wherein reading comprises successively adjusting an adjustable current source to cause the adjustable current source to output the corresponding reference currents from the set of N-1 reference currents.
4 . The method according to claim 1 , wherein the multi-level non-volatile memory cell is a phase-change type memory cell.
5 . The method according to claim 1 , wherein the multi-level non-volatile memory cell is a phase-change type memory cell, wherein a reference memory cell that is structurally identical to the multi-level non-volatile memory cell is placed next to the multi-level non-volatile memory cell, wherein the reference memory cell is a phase-change memory cell, wherein reading comprises successively reading the reference memory cell to cause the reference memory cell to output the corresponding reference currents from the set of N-1 reference currents, and further comprising:
placing the reference memory cell in a SET state and applying a selected reference voltage to the reference memory cell to cause it to output the corresponding reference current.
6 . The method according to claim 1 , further comprising programming the multi-level non-volatile memory cell to the desired level and checking the programming by using said reading of the multi-level non-volatile memory cell.
7 . The method according to claim 1 , wherein the multi-level non-volatile memory cell is a phase-change type memory cell, wherein programming the multi-level non-volatile memory cell to a level lower than a maximum level comprises programming the multi-level non-volatile memory cell to the maximum level, then successively outputting erase pulses erasing the multi-level non-volatile memory cell, respectively followed by successively reading the multi-level non-volatile memory cell until a read current corresponding to the desired programming level is reached.
8 . A multi-level non-volatile memory device, comprising:
at least one non-volatile memory cell having N levels, N being even and greater than two, corresponding respectively to N logical data that can be stored in the multi-level non-volatile memory cell and to N corresponding read current ranges; and
a reading circuit configured to read a datum stored in the multi-level non-volatile memory cell by carrying out successive comparisons of a read current output by the multi-level non-volatile memory cell with reference currents selected from a set of N-1 reference currents having values respectively lying between two different successive ranges using a dichotomous algorithm starting with the reference current having the median value.
9 . The device according to claim 8 , wherein the reading circuit comprises:
a reference memory cell located next to the multi-level non-volatile memory cell and structurally identical to the multi-level non-volatile memory cell; and
a read module configured to perform successive readings of the reference memory cell to cause the reference memory cell to output the corresponding reference currents.
10 . The device according to claim 8 , wherein the reading circuit comprises:
an adjustable current source; and
a control circuit configured to make successive adjustments to the current source to cause it to output successively selected reference currents.
11 . The device according to claim 8 , wherein the multi-level non-volatile memory cell is a phase-change type memory cell.
12 . The device according to claim 8 , wherein the multi-level non-volatile memory cell is a phase-change type memory cell; wherein the phase-change type reference memory cell is programmed in a SET state; wherein the reading circuit comprises:
a reference memory cell located next to the multi-level non-volatile memory cell and structurally identical to the multi-level non-volatile memory cell; and
a read module configured to perform successive readings of the reference memory cell to cause the reference memory cell to output the corresponding reference currents; and
wherein the read module is configured to apply a selected reference voltage to the reference memory cell to cause it to output the corresponding reference current.
13 . The device according to claim 8 , further comprising:
a processing circuit configured to program the multi-level non-volatile memory cell to the desired level; and
wherein the reading circuit is configured to check the programming by reading the multi-level non-volatile memory cell.
14 . The device according to claim 8 , wherein the multi-level non-volatile memory cell is a phase-change type memory cell, further comprising:
a processing circuit configured to program the multi-level non-volatile memory cell to the desired level; and
wherein the reading circuit is configured to check the programming by reading the multi-level non-volatile memory cell; and
wherein the processing circuit is configured to program the multi-level non-volatile memory cell to a level lower than a maximum level by programming the multi-level non-volatile memory cell to the maximum level, then by successively outputting erase pulses erasing the multi-level non-volatile memory cell, respectively followed by successively reading the multi-level non-volatile memory cell until a read current corresponding to the desired programming level is reached.
15 . A method for managing the operation of a multi-level non-volatile memory cell, wherein the multi-level non-volatile memory cell is a phase change type memory cell having N levels, N being greater than or equal to two, corresponding respectively to N logical data likely to be stored in the multi-level non-volatile memory cell and N corresponding read current ranges, the method comprising:
reading the logical data stored in the multi-level non-volatile memory cell with successive comparisons a read current delivered by the multi-level non-volatile memory cell with reference currents chosen from a set of N-1 reference currents having values respectively located between two different successive ranges;
wherein reading uses a dichotomous algorithm starting with the reference current having the median value;
placing, next to the multi-level non-volatile memory cell, a reference memory cell with a phase change structurally identical to the multi-level non-volatile memory cell; and
successively reading this reference memory cell to cause delivery of corresponding reference currents;
wherein delivery of a reference current comprises placing the reference memory cell in an initialized state and applying a selected reference voltage to the reference memory cell to cause delivery of the corresponding reference current.
16 . The method of claim 15 further comprising: programming the multi-level non-volatile memory cell at a desired programming level and verifying programming at the desired level reading said multi-level non-volatile memory cell.
17 . The method of claim 16 , wherein programming comprises programming the multi-level non-volatile memory cell at a desired programming level below a maximum programming level by programming the multi-level non-volatile memory cell at the maximum programming level and then successively delivering erasure pulses to the multi-level non-volatile memory cell respectively followed by successive reads of the multi-level non-volatile memory cell until a read current corresponding to the desired programming level is reached.
18 . A multi-level non-volatile memory device, comprising:
at least one multi-level non-volatile memory cell;
wherein the multi-level non-volatile memory cell is a phase change type memory cell having N levels, N being greater than or equal to two, corresponding respectively to N logical data likely to be stored in the multi-level non-volatile memory cell and N corresponding read current ranges;
a circuit for reading data stored in the multi-level non-volatile memory cell, wherein said circuit is configured to perform successive comparisons of a read current delivered by the multi-level non-volatile memory cell with reference currents selected from a set of N-1 reference currents having values respectively located between two different successive ranges, using a dichotomous algorithm starting with the reference current having the median value in which the circuit for reading comprises:
a reference memory cell of phase change type, located next to the multi-level non-volatile memory cell and structurally identical to the multi-level non-volatile memory cell; and
a read module configured to perform successive reads of said reference memory cell to deliver corresponding reference currents;
wherein the reference memory cell is programmed in an initialized state and the read module is configured to apply a reference voltage to the reference memory cell to cause delivery of the corresponding reference current.
19 . The apparatus of claim 18 , further comprising a processing circuit configured to perform a programming of the multi-level non-volatile memory cell at a desired programming level and to perform a programming check by reading said multi-level non-volatile memory cell.
20 . The apparatus of claim 19 , wherein the processing circuit is configured to perform memory cell programming at a desired programming level below a maximum programming level by programming the multi-level non-volatile memory cell at the maximum programming level and then performing successive deliveries of memory cell erasure pulses respectively followed by successive reads from the multi-level non-volatile memory cell until reaching a read current corresponding to the desired programming level.