SYNCHRONIZATION IN A QUANTUM CONTROLLER WITH MODULAR AND DYNAMIC PULSE GENERATION AND ROUTING
A quantum controller comprises a first quantum control pulse generation circuit and a second quantum control pulse generation circuit. The first quantum control pulse generation circuit and a second quantum control pulse generation circuit are operable to operate asynchronously during some time intervals of a quantum algorithm and synchronously during other time intervals of the quantum algorithm.
1 - 19 . (canceled)
20 . A system comprising:
a first pulse generation circuit operable to generate a first pulse; and
a second pulse generation circuit operable to generate a second pulse, wherein:
the first pulse generation circuit and the second pulse generation circuit are selectively synchronized, and
when the first pulse generation circuit and the second pulse generation circuit are synchronized, a timing of the first pulse and the second pulse is determined according to a synchronization register.
21 . The system of claim 20 , wherein the timing of the first pulse and the second pulse is determined according to a wait time register.
22 . The system of claim 20 , wherein a wait time register is set according to how long it takes signals to propagate to the first pulse generation circuit and/or the second pulse generation circuit.
23 . The system of claim 20 , wherein:
the system is operable to change from synchronous to asynchronous in response to a synchronization field of an instruction.
24 . The system of claim 20 , wherein the second pulse generation circuit is operable to wait for a number of clock cycles.
25 . The system of claim 20 , wherein the second pulse generation circuit is operable to wait according to an uncertainty in how long it takes signals to propagate to the second pulse generation circuit and/or the first pulse generation circuit.
26 . The system of claim 20 , wherein the first pulse generation circuit is operable to wait for a next on-grid clock cycle before triggering a change of a state of synchronization.
27 . The system of claim 20 , wherein the first pulse generation circuit is operable to wait N clock cycles before triggering a change of state of synchronization.
28 . The system of claim 20 , wherein the system comprises a synchronization management circuit that is in a first state for 1 out of every N clock cycles and is not in the first state for N−1 of every N clock cycles.
29 . The system of claim 28 , wherein a value of N is based on a value stored in a grid-step register of the synchronization management circuit.
30 . A method comprising:
selecting between synchronous and asynchronous pulse generation;
generating a first pulse; and
generating a second pulse, wherein:
during synchronous pulse generation, a timing of the first pulse and the second pulse is determined according to a synchronization register.
31 . The method of claim 30 , wherein the method comprises:
determining timing of the first pulse and the second pulse according to a wait time register.
32 . The method of claim 30 , wherein the method comprises:
setting a wait time register according to how long it takes signals to propagate to the first pulse generation circuit and/or the second pulse generation circuit.
33 . The method of claim 30 , wherein the method comprises:
changing from synchronous to asynchronous in response to a synchronization field of an instruction.
34 . The method of claim 30 , wherein the method comprises:
waiting for a number of clock cycles before generating the second pulse.
35 . The method of claim 30 , wherein the method comprises:
waiting according to an uncertainty in how long it takes signals to propagate to a second pulse generation circuit and/or a first pulse generation circuit.
36 . The method of claim 30 , wherein the method comprises:
waiting for a next on-grid clock cycle before triggering a change of a state of synchronization.
37 . The method of claim 30 , wherein the method comprises:
waiting for N clock cycles before triggering a change of state of synchronization.
38 . The method of claim 30 , wherein the method comprises:
maintaining a first state of synchronization for 1 out of every N clock cycles.
39 . The method of claim 38 , wherein a value of N is based on a stored value.