Memory circuit architecture with multiplexing between memory banks
One implementation includes a random access memory (RAM) that has a muted multiplexing functionality. For instance, a RAM may be implemented having a first outer bank, a first inner bank, a second outer bank, and a second inner bank, each coupled to a controller. Multiplexing circuits for the outer banks may be disposed adjacent the outer banks and away from the controller, whereas the multiplexing circuits for the inner banks may be disposed within or adjacent to the controller.
1 . A system on chip (SOC) comprising:
a random-access memory (RAM) having a first inner memory bank, a first outer memory bank, a second inner memory bank, and a second outer memory bank, wherein the first inner memory bank is positioned between the first outer memory bank and a controller of the RAM, and wherein the second inner memory bank is positioned between the second outer memory bank and the controller of the RAM;
a distributed multiplexer system within the RAM, including a first outer multiplexer disposed on a first side of the first inner memory bank opposite the controller, a first inner multiplexer disposed between the first inner memory bank and a write driver and a sense amplifier of the controller of the RAM, a second inner multiplexer disposed between the second inner memory bank and the write driver and sense amplifier, and a second outer multiplexer disposed on a second side of the second inner memory bank opposite the controller;
a first plurality of data lines coupling the controller to the first outer multiplexer; and
a second plurality of data lines coupling the controller to the first inner multiplexer.
2 . The SOC of claim 1 , wherein the first plurality of data lines traverse the first inner memory bank, and the second plurality of data lines are physically shorter than the first plurality of data lines.
3 . The SOC of claim 1 , further comprising:
a first plurality of bit lines coupling the first outer multiplexer to columns within the first outer memory bank.
4 . The SOC of claim 1 , further comprising:
a third plurality of data lines coupling the controller to the second outer multiplexer, the third plurality of data lines traversing the second inner memory bank.
5 . The SOC of claim 4 , further comprising:
a fourth plurality of data lines coupling the controller to the second inner multiplexer, the fourth plurality of data lines being physically shorter than the third plurality of data lines.
6 . The SOC of claim 4 , further comprising:
a second plurality of bit lines coupling the second outer multiplexer to columns within the second outer memory bank.
7 . The SOC of claim 1 , wherein the first plurality of data lines includes a first read data line and a first write data line, wherein the first read data line has a different width than does the first write data line.
8 . The SOC of claim 1 , wherein the first outer multiplexer includes a first read multiplexer and a first write multiplexer, and wherein the first inner multiplexer includes a second read multiplexer and a second write multiplexer.
9 . The SOC of claim 8 , wherein the second outer multiplexer includes a third read multiplexer and a third write multiplexer, and wherein the second inner multiplexer includes a fourth read multiplexer and a fourth write multiplexer.
10 . The SOC of claim 1 , wherein the first inner multiplexer and the second inner multiplexer are both disposed within the controller.
11 . The SOC of claim 1 , further comprising:
a first local data path associated with the first outer memory bank, the first local data path including a first precharge circuit and the first outer multiplexer; and
a second local data path associated with the first inner memory bank, the second local data path including a second precharge circuit and the first inner multiplexer.