Integrated circuit
An integrated circuit may include two processing cores. Each processing core may include: a core controller operable to execute instructions to perform processing tasks; a memory resource connected to the core controller; and a hardware accelerator module connected to the core controller. The integrated circuit may further include: a shared bus connected to the respective hardware accelerator modules of the two processing cores; and a shared memory resource connected to the shared bus; where the only communication path between the two processing cores is via the hardware accelerator modules and the shared bus.
1 . An integrated circuit comprising:
two processing cores, wherein each processing core of the two processing cores comprises:
a core controller operable to execute instructions to perform one or more processing tasks;
a memory resource connected to the core controller; and
a hardware accelerator module connected to the core controller, wherein the hardware accelerator module only obtains data from the memory resource via the core controller, wherein the core controller is configured to send an instruction signal to the hardware accelerator module via an interface, wherein the core controller is configured to send a verification signal to the hardware accelerator module to verify that the instruction signal is a valid signal;
a shared bus connected to a respective hardware accelerator module of the two processing cores, wherein each hardware accelerator module of the two processing cores is configured to perform one or more cryptographic operations to encrypt the data provided by a respective core controller before forwarding the encrypted data to the shared bus; and
a shared memory resource connected to the shared bus,
wherein the only communication path between the two processing cores is via the hardware accelerator modules and the shared bus.
2 . The integrated circuit of claim 1 , wherein the two processing cores are heterogeneous.
3 . The integrated circuit of claim 2 , wherein a clock frequency of a first processing core of the two processing cores is faster than a clock frequency of a second processing core of the two processing cores.
4 . The integrated circuit of claim 1 , further comprising: two isolated subsystems;
wherein each processing core of the two processing cores is associated with a respective subsystem of the two isolated subsystems;
wherein each subsystem comprises a dedicated system bus configured to connect a respective associated processing core to one or more components of the subsystem; and
wherein the dedicated system bus of a first subsystem of the two isolated subsystems is isolated from the dedicated system bus of a second subsystem of the two isolated subsystems.
5 . The integrated circuit of claim 4 , wherein each dedicated system bus is connected to the respective associated processing core by means of a crossbar connection.
6 . The integrated circuit of claim 4 , wherein the first subsystem of the two isolated subsystems further comprises an external memory bus configured to be connected to an external memory resource.
7 . The integrated circuit of claim 4 , wherein the second subsystem of the two isolated subsystems further comprises a peripherals bus configured to be connected to one or more peripheral resources.
8 . The integrated circuit of claim 1 , wherein the memory resource of each processing core comprises a data memory resource and an instruction memory resource.
9 . The integrated circuit of claim 8 , wherein the data memory resource is a tightly integrated data memory.
10 . The integrated circuit of claim 8 , wherein the instruction memory resource is a tightly integrated instruction memory.
11 . The integrated circuit of any claim 1 , wherein the hardware accelerator module of each processing core is configured to execute instructions from the RISC-V instruction set.
12 . The integrated circuit of claim 11 , wherein the hardware accelerator module of each processing core is configured to communicate with an associated processing core using a custom instruction interface.
13 . The integrated circuit of claim 1 , wherein the hardware accelerator module is configured to provide data from the memory resource of a first processing core of the two processing cores to the shared memory resource via the shared bus.
14 . The integrated circuit of claim 13 , wherein the hardware accelerator module is further configured to send an interrupt signal to a second processing core of the two processing cores to indicate that new data is available in the shared memory resource.