FULLY HOMOMORPHIC ENCRYPTED PROCESSING ACCELERATION
A method for conflict-free memory accesses comprises storing data in a memory. The memory can be accessed by row or column, and the data is arranged in a scrambled ordering. Further, the process includes defining a bank as a specified row exclusive or-ed with a specific column. When addressing a row, mapping a bank i to an index i xor the row. On the other hand, when addressing a column, mapping a bank i to an index i xor the row.
1 . A method for conflict-free memory accesses, the method comprising:
storing data in a single-port memory, wherein:
the memory can be accessed by row or column; and
the data is arranged in a scrambled ordering;
defining a bank as a specified row exclusive or-ed with a specific column;
when addressing a row, mapping a bank i to an index i xor the row; and
when addressing a column, mapping a bank i to an index i xor the row.
2 . The method of claim 1 , further comprising:
using permutation processing elements to reorder the data from the memory.
3 . The method of claim 2 , wherein the memory is accessed via a single-cycle operation per chunk, wherein a chunk is defined as a number of coefficients to be accessed per cycle.
4 . The method of claim 3 , wherein using permutation processing elements to reorder the data from the memory comprises:
when addressing a row, a chunk of data is received from the columns.
5 . The method of claim 3 , wherein using permutation processing elements to reorder the data from the memory comprises:
when addressing a column, a chunk of data is received from the rows.
6 . The method of claim 2 , wherein:
the permutation processing elements includes a network of conditional step nodes, wherein the number of conditional step nodes is related to a size of the permutation processing element.
7 . The method of claim 2 , wherein:
the permutation processing elements includes a network of conditional step nodes, where the conditional swap nodes either swap inputs or keep the inputs the same based on a control value.
8 . The method of claim 1 , wherein an address bit determines whether the memory is to be accessed to address a row or column.