IP Library › Granted Patent US 12,299,282
Granted Patent B2
US 12,299,282 · App. 18/675,934 · Granted May 13, 2025

Runtime storage capacity reduction avoidance in sequentially-written memory devices

Inventors: Vinay Vijendra Kumar Lakshmi (Karnataka, IN); Vijaya Janarthanam (Karnataka, IN)
Assignee: Micron Technology, Inc.
G06F3/0608G06F3/064G06F3/0653G06F3/0659G06F3/0679
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,299,282
App. No.
18/675,934
Granted
May 13, 2025
Kind
B2
Abstract

A system includes a memory device having a plurality of blocks. A first subset of the plurality of blocks is configured as single-level cell (SLC) memory and a second subset of the plurality of blocks is configured as multi-level cell (MLC) memory. A processing device, operatively coupled to the memory device, determines that a first block of a set of blocks of the first subset is a bad block, wherein the first block is located in a first plane of the memory device. The processing device converts a second block of the set of blocks to the MLC memory of the second subset, wherein the second block is located in a second plane of the memory device, and wherein the second plane is neighboring the first plane.

Claims (40)

1. A system comprising:

a memory device comprising a plurality of blocks, wherein a first subset of the plurality of blocks is configured as single-level cell (SLC) memory and a second subset of the plurality of blocks is configured as multi-level cell (MLC) memory; and

a processing device operatively coupled to the memory device, the processing device to perform operations comprising:

determining that a first block of a set of blocks of the first subset is a bad block, wherein the first block is located in a first plane of the memory device; and

converting a second block of the set of blocks to the MLC memory of the second subset, wherein the second block is located in a second plane of the memory device, and wherein the second plane is neighboring the first plane.

2. The system of claim 1 , wherein the operations further comprise converting a media endurance metric value of the second block from SLC-type to MLC-type, and wherein the determining and the converting the second block and the media endurance metric value are performed during runtime while directing program or erase operations at the memory device.

3. The system of claim 2 , wherein converting the media endurance metric value comprising tracking the media endurance metric value over time as a program/erase cycle (PEC) value.

4. The system of claim 3 , wherein converting the media endurance metric value comprises using an MLC conversion factor to convert a PEC value for the second block from SLC-type PEC to MLC-type PEC.

5. The system of claim 1 , wherein converting the second block to MLC memory comprises causing an MLC erase operation to be performed on the second block.

6. The system of claim 1 , wherein determining that the first block is a bad block comprises determining that the first block is one of a grown bad block or a manufactured bad block.

7. The system of claim 1 , wherein the determining further comprises determining that the second block is not a bad block.

8. The system of claim 1 , wherein the second block is a converted MLC block and the operations further comprise:

detecting an MLC block of the second subset has failed; and

assigning the converted MLC block to be a target block for relocating data stored at the MLC block, to avoid a zone that includes the MLC block from going offline.

9. A method comprising:

accessing, by a processing device, a memory device comprising a plurality of blocks, wherein a first subset of the plurality of blocks is configured as single-level cell (SLC) memory and a second subset of the plurality of blocks is configured as multi-level cell (MLC) memory;

determining that a first block of a set of blocks of the first subset is a bad block, wherein the first block is located in a first plane of the memory device; and

converting a second block of the set of blocks to the MLC memory of the second subset, wherein the second block is located in a second plane of the memory device, and wherein the second plane is neighboring the first plane.

10. The method of claim 9 , further comprising converting, by the processing device, a media endurance metric value of the second block from SLC-type to MLC-type, wherein the determining and the converting the second block and the media endurance metric value are performed during runtime while directing program or erase operations to be performed at the memory device.

11. The method of claim 10 , further comprising tracking the media endurance metric value over time as a program/erase cycle (PEC) value.

12. The method of claim 11 , wherein converting the media endurance metric value comprises using an MLC conversion factor to convert a PEC value for the second block from SLC-type PEC to MLC-type PEC.

13. The method of claim 9 , wherein converting the second block to MLC memory comprises causing an MLC erase operation to be performed on the second block.

14. The method of claim 9 , wherein determining that the first block is a bad block comprises determining that the first block is one of a grown bad block or a manufactured bad block.

15. The method of claim 9 , wherein the determining further comprises determining that the second block is not a bad block.

16. The method of claim 9 , wherein the second block is a converted MLC block, the method further comprising:

detecting an MLC block of the second subset has failed; and

assigning the converted MLC block to be a target block for relocating data stored at the MLC block.

17. A non-transitory computer-readable storage medium storing instructions, which when executed by a processing device, cause the processing device to perform operations comprising:

accessing a memory device comprising a plurality of blocks, wherein a first subset of the plurality of blocks is configured as single-level cell (SLC) memory and a second subset of the plurality of blocks is configured as multi-level cell (MLC) memory;

determining that a first block of a set of blocks of the first subset is a bad block, wherein the first block is located in a first plane of the memory device; and

converting a second block of the set of blocks to the MLC memory of the second subset, wherein the second block is located in a second plane of the memory device, and wherein the second plane is neighboring the first plane.

18. The non-transitory computer-readable storage medium of claim 17 , wherein the operations further comprise:

converting the second block and a media endurance metric value of the second block from SLC-type to MLC-type, wherein the determining and the converting are performed during runtime while directing program or erase operations at the memory device; and

tracking the media endurance metric value over time as a program/erase cycle (PEC) value, wherein:

converting the media endurance metric value comprises using an MLC conversion factor to convert a PEC value for the second block from SLC-type PEC to MLC-type PEC; and

converting the second block to MLC memory comprises causing an MLC erase operation to be performed on the second block.

19. The non-transitory computer-readable storage medium of claim 17 , wherein determining that the first block is a bad block comprises determining that the first block is one of a grown bad block or a manufactured bad block and that the second block is not a bad block.

20. The non-transitory computer-readable storage medium of claim 17 , wherein the second block is a converted MLC block and the operations further comprise:

detecting an MLC block of the second subset has failed; and

assigning the converted MLC block to be a target block for relocating data stored at the MLC block.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 2, 2025
From: LAKSHMI, VINAY VIJENDRA KUMAR; JANARTHANAM, VIJAYA
To: MICRON TECHNOLOGY, INC.
Reel/Frame 069725/0919 →
Continuity (2)
Continuation 17976241 · Oct 28, 2022
Related Publication 20240311004A1 · Sep 19, 2024
References Cited (4)
US 9477587B2 · Wong · 2016 [cited by examiner]
US 11373729B2 · Liu · 2022 [cited by examiner]
US 11556479B1 · He · 2023 [cited by examiner]
US 11605439B2 · Bhardwaj · 2023 [cited by examiner]