Method and System for In-NAND Checksum Calculating of LDPC Codes

1 . A method for calculating checksums in a controller inside a memory device, comprising:

selecting a subset matrix derived from an error correction code (ECC) parity-check matrix used in the controller; and

performing a partial checksum calculation using the subset matrix to estimate bit error rate (BER).

2 . The method of claim 1 , further comprising:

performing the partial checksum calculation utilizing a gate-count efficient syndrome calculator module which resides close to the memory device where actual data is stored.

3 . The method of claim 1 , wherein the performing the partial checksum calculation comprises utilizing quasi-cyclic codes comprising circulant layers selected from the ECC parity-check matrix, each circulant layer comprising a group of check nodes, thereby reducing a gate count for the gate-count efficient syndrome calculator module.

4 . The method of claim 1 , wherein the subset matrix has fewer check nodes than the ECC parity-check matrix.

5 . The method of claim 4 , wherein the ECC parity-check matrix comprises m check nodes and the subset matrix has a reduced number of check nodes ranging from m/2 to m/8.

6 . The method of claim 1 , wherein the partial checksum calculation is calculated using a punctured set of parity bits.

7 . The method of claim 6 , wherein the performing a partial checksum calculation selects circulant layers that do not have nonzero elements corresponding to punctured parity bits.

8 . The method of claim 7 , wherein the performing a partial checksum calculation comprises calculating checksums by counting non-zero syndrome bits for columns in the circulant layers.

9 . The method of claim 7 , wherein the performing a partial checksum calculation comprises providing the checksum calculator with code generation constraints identifying which entries of the ECC parity-check matrix are used when more than one circulant layer is used.

10 . The method of claim 1 , wherein, prior to the performing a partial checksum calculation, converting a shift value, representing bit shifts between different circulant layers, to zero for all nonzero circulant layers.

11 . The method of claim 1 , wherein

the performing a partial checksum calculation calculates checksums on scrambled-encoded data read from a buffer of the storage of the memory system, and

the scrambled-encoded data has information bits of the codeword data randomized.

12 . A memory system, comprising:

a storage; and

a checksum calculator in the storage, the checksum calculator including a gate-count efficient syndrome calculator module and configured to:

select a subset matrix from an error correction code (ECC) parity-check matrix used in a controller of the storage, and

perform a partial checksum calculation using the subset matrix to estimate bit error rate (BER) utilizing the gate-count efficient syndrome calculator module.

13 . The memory system of claim 12 , wherein the checksum calculator comprises:

a first input for receiving codeword data;

a second input for receiving information on selecting the subset matrix from the ECC parity-check matrix.

14 . The memory system of claim 12 , wherein

the checksum calculator is configured to perform partial checksum calculations on the codeword data, and

the partial checksum calculations estimate the BER in the codeword data.

15 . The memory system of claim 14 , wherein the checksum calculator in performing the partial checksum calculations is configured to utilize the subset matrix having fewer check nodes than the ECC parity-check matrix.

16 . The memory system of claim 15 , wherein the ECC parity-check matrix comprises m check nodes and the subset matrix has a reduced number of check nodes ranging from m/2 to m/8.

17 . The memory system of claim 15 , wherein the partial checksum is calculated using a punctured set of parity bits.

18 . The memory system of claim 12 , wherein the checksum calculator in performing the partial checksum calculations with the gate-count efficient syndrome calculator module is configured to utilize quasi-cyclic codes comprising circulant layers selected from the ECC parity-check matrix, each circulant layer comprising a group of check nodes.

19 . The memory system of claim 18 , wherein the checksum calculator in performing the partial checksum calculations is configured to calculate checksums by counting non-zero syndrome bits for columns in the circulant layers.

20 . The memory system of claim 12 , wherein, prior to the checksum calculator performing the partial checksum calculations, a shift value, representing bit shifts between different circulant layers, is converted to zero for all nonzero circulant layers.

21 . The memory system of claim 12 , wherein

the checksum calculator is configured to calculate checksums on scrambled-encoded data read from a buffer of the storage of the memory system, and

the scrambled-encoded data has information bits of the codeword data randomized.

22 . A NAND memory device comprising:

a NAND storage; and

a system on chip processor configured to process data exchanged between a host and the NAND storage,

wherein

the NAND storage includes therein a checksum calculator including a gate-count efficient syndrome calculator module.

the checksum calculator is configured to:

select a subset matrix from an error correction code (ECC) parity-check matrix used in a controller of the NAND storage, and

perform a partial checksum calculation using the subset matrix to estimate bit error rate (BER) utilizing the gate-count efficient syndrome calculator module.