Streaming scan network latency balancing to reduce cost of testing identical replicated blocks
Certain aspects of the present disclosure provide techniques and apparatus for latency balancing in a streaming scan network (SSN) on an integrated circuit. Embodiments include receiving, at a programmable block on the integrated circuit, an indication of a number of pipeline stages to be used for a test operation in the SSN. Embodiments include selecting, by the programmable block, based on the indication, a subset of a plurality of pipeline stages in the programmable block using a multiplexer. Embodiments include balancing latency throughout the SSN on the integrated circuit based on the selected subset of the plurality of pipeline stages in the programmable block.
1 . A method for latency balancing in a streaming scan network (SSN) on an integrated circuit, comprising:
receiving, at a programmable block on the integrated circuit, an input numerical value indicating a number of pipeline stages to be used for a test operation in the SSN;
selecting, by the programmable block, based on the input numerical value, a subset of a plurality of pipeline stages in the programmable block using a multiplexer, wherein each pipeline stage of the plurality of pipeline stages comprises a sequential element with a clock, an input, and an output; and
balancing latency throughout the SSN on the integrated circuit based on the selected subset of the plurality of pipeline stages in the programmable block.
2 . The method of claim 1 , wherein the selecting is based on populating one or more registers in the programmable block with the number of pipeline stages to be used for the test operation in the SSN.
3 . The method of claim 1 , wherein the programmable block includes the plurality of pipeline stages for inputs to the SSN and an additional plurality of pipeline stages for outputs from the SSN.
4 . The method of claim 1 , wherein the programmable block is configured to use the plurality of pipeline stages as either input pipeline stages or output pipeline stages.
5 . The method of claim 1 , wherein the number of pipeline stages corresponds to a number of inputs to a given processor core in the integrated circuit that has a largest number of inputs of a plurality of processor cores tested in the SSN.
6 . The method of claim 1 , wherein the programmable block is located outside of a section of the integrated circuit that is tested by the SSN.
7 . The method of claim 1 , wherein the SSN comprises a bypass path that enables test data to be transmitted through the SSN while bypassing one or more processor cores connected to a data bus of the SSN.
8 . The method of claim 1 , wherein the selecting, by the programmable block, based on the indication, the subset of the plurality of pipeline stages in the programmable block using the multiplexer enables a same test pattern to be applied to each of a plurality of identical replicated blocks tested by the SSN.
9 . The method of claim 1 , wherein the plurality of pipeline stages are implemented as a latch array.
10 . A processing system comprising:
one or more memories comprising processor-executable instructions; and
one or more processors configured to execute the processor-executable instructions and cause the processing system to:
receive, at a programmable block on an integrated circuit, an input numerical value indicating a number of pipeline stages to be used for a test operation in a streaming scan network (SSN) on the integrated circuit;
select, by the programmable block, based on the input numerical value, a subset of a plurality of pipeline stages in the programmable block using a multiplexer, wherein each pipeline stage of the plurality of pipeline stages comprises a sequential element with a clock, an input, and an output; and
balance latency throughout the SSN on the integrated circuit based on the selected subset of the plurality of pipeline stages in the programmable block.
11 . The processing system of claim 10 , wherein the selecting is based on populating one or more registers in the programmable block with the number of pipeline stages to be used for the test operation in the SSN.
12 . The processing system of claim 10 , wherein the programmable block includes the plurality of pipeline stages for inputs to the SSN and an additional plurality of pipeline stages for outputs from the SSN.
13 . The processing system of claim 10 , wherein the programmable block is configured to use the plurality of pipeline stages as either input pipeline stages or output pipeline stages.
14 . The processing system of claim 10 , wherein the number of pipeline stages corresponds to a number of inputs to a given processor core in the integrated circuit that has a largest number of inputs of a plurality of processor cores tested in the SSN.
15 . The processing system of claim 10 , wherein the programmable block is located outside of a section of the integrated circuit that is tested by the SSN.
16 . The processing system of claim 10 , wherein the SSN comprises a bypass path that enables test data to be transmitted through the SSN while bypassing one or more processor cores connected to a data bus of the SSN.
17 . The processing system of claim 10 , wherein the selecting, by the programmable block, based on the indication, the subset of the plurality of pipeline stages in the programmable block using the multiplexer enables a same test pattern to be applied to each of a plurality of identical replicated blocks tested by the SSN.
18 . The processing system of claim 10 , wherein the plurality of pipeline stages are implemented as a latch array.
19 . An apparatus, comprising:
means for receiving, at a programmable block on an integrated circuit, an input numerical value indicating a number of pipeline stages to be used for a test operation in a streaming scan network (SSN) on the integrated circuit;
means for selecting, by the programmable block, based on the input numerical value, a subset of a plurality of pipeline stages in the programmable block using a multiplexer, wherein each pipeline stage of the plurality of pipeline stages comprises a sequential element with a clock, an input, and an output; and
means for balancing latency throughout the SSN on the integrated circuit based on the selected subset of the plurality of pipeline stages in the programmable block.
20 . The apparatus of claim 19 , wherein the selecting is based on populating one or more registers in the programmable block with the number of pipeline stages to be used for the test operation in the SSN.