SELECTIVE ACCESS FOR GROUPED MEMORY DIES
Methods, systems, and devices for selective access for grouped memory dies are described. A memory device may be configured with a select die access protocol for a group of memory dies that share a same channel. The protocol may be enabled by one or more commands from the host device, which may be communicated to each of the memory dies of the group via the channel. The command(s) may indicate a first set of one or more memory dies of the group for which a set of commands may be enabled and may also indicate a second set of one or more memory dies of the group for which at least a subset of the set of commands is disabled. When the select die access mode is enabled, the disabled memory dies may be restricted from performing the subset of commands received via the channel.
1 . (canceled)
2 . A memory device, comprising:
a command/address channel;
one or more data channels; and
a plurality of memory dies, each memory die of the plurality of memory dies comprising a first electrical connection associated with coupling the respective memory die with the command/address channel and a second electrical connection associated with coupling the respective memory die with a data channel of the one or more data channels.
3 . The memory device of claim 2 , wherein each memory die of the plurality of memory dies is directly coupled with the command/address channel via a respective first electrical connection associated with the respective memory die.
4 . The memory device of claim 2 , wherein a first memory die of the plurality of memory dies is directly coupled with the command/address channel via a first electrical connection associated with the first memory die, and
wherein the plurality of memory dies excluding the first memory die are indirectly coupled with the command/address channel based at least in part on respective first electrical connections associated with the plurality of memory dies being coupled with the first electrical connection associated with the first memory die.
5 . The memory device of claim 2 , wherein each memory die is directly coupled with a respective data channel of the one or more data channels via a respective second electrical connection associated with the respective memory die.
6 . The memory device of claim 2 , wherein a first subset of the plurality of memory dies is coupled with a first data channel of the one or more data channels, and wherein a second subset of the plurality of memory dies is coupled with a second data channel of the one or more data channels.
7 . The memory device of claim 6 , wherein a first memory die of the first subset is directly coupled with the first data channel via a second electrical connection associated with the first memory die, and
wherein one or more memory dies of the first subset are indirectly coupled with the first data channel based at least in part on the respective second electrical connections associated with the one or more memory dies being coupled with the second electrical connection associated with the first memory die.
8 . The memory device of claim 2 , further comprising:
a plurality of registers, each register of the plurality of registers associated with a respective memory die of the plurality of memory dies.
9 . The memory device of claim 8 , wherein each register of the plurality of registers is configured to store:
a first indication of a respective data channel associated with the respective memory die;
a second indication that the respective memory die is directly or indirectly coupled with the respective data channel; and
a third indication of a status of the respective memory die, wherein the status indicates that the respective memory die is enabled or disabled for a select die access mode.
10 . The memory device of claim 2 , wherein the command/address channel is configured to communicate a select die access command between the memory device and a host device, and wherein the select die access command is associated with enabling one or more memory dies of the plurality of memory dies to perform one or more select access operations.
11 . The memory device of claim 2 , wherein the one or more data channels are configured to communicate data between the memory device and a host device.
12 . The memory device of claim 2 , wherein the plurality of memory dies are associated with a group of one or more groups associated with a rank of one or more ranks of the memory device.
13 . A memory device, comprising:
a command/address channel;
a first data channel;
a second data channel;
a first memory die comprising a first electrical connection associated with coupling the first memory die with the command/address channel and a second electrical connection associated with coupling the first memory die with the first data channel; and
a second memory die comprising a third electrical connection associated with coupling the second memory die with the command/address channel and a fourth electrical connection associated with coupling the second memory die with the second data channel.
14 . The memory device of claim 13 , further comprising:
a third memory die comprising a fifth electrical connection associated with coupling the third memory die with the command/address channel and a sixth electrical connection associated with coupling the third memory die with the first data channel; and
a fourth memory die comprising a seventh electrical connection associated with coupling the fourth memory die with the command/address channel and an eighth electrical connection associated with coupling the fourth memory die with the second data channel.
15 . The memory device of claim 14 , wherein the third memory die is directly coupled with the first data channel via the sixth electrical connection, and wherein the fourth memory die is directly coupled with the second data channel via the eighth electrical connection.
16 . The memory device of claim 14 , wherein the first memory die is directly coupled with the first data channel via the second electrical connection, and wherein the third memory die is indirectly coupled with the first data channel based at least in part on the sixth electrical connection being coupled with the second electrical connection.
17 . The memory device of claim 14 , wherein the second memory die is directly coupled with the second data channel via the fourth electrical connection, and wherein the fourth memory die is indirectly coupled with the second data channel based at least in part on the eighth electrical connection being coupled with the fourth electrical connection.
18 . The memory device of claim 13 , wherein the first memory die is directly coupled with the command/address channel via the first electrical connection, and wherein the second memory die is directly coupled with the command/address channel via the third electrical connection.
19 . The memory device of claim 13 , wherein the first memory die is directly coupled with the command/address channel via the first electrical connection, and wherein the second memory die is indirectly coupled with the command/address channel based at least in part on the third electrical connection being coupled with the first electrical connection.
20 . The memory device of claim 13 , further comprising:
a first register associated with the first memory die; and
a second register associated with the second memory die.
21 . The memory device of claim 20 , wherein the first register is configured to store:
a first indication of the first data channel;
a second indication that the first memory die is directly or indirectly coupled with the first data channel; and
a third indication of a status of the first memory die, wherein the status indicates that the first memory die is enable or disabled for a select die access mode.