IP Library › Patent Application 18688534
Patent Application
App. No. 18/688,534

Optical Inspection Circuit and Method of Manufacturing an Optical Circuit Chip

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Quick Facts
Patent No.
US None
App. No.
18/688,534
Abstract

The present invention is intended to provide an inspection optical circuit that can input and output inspection light to and from a circuit to be inspected with low loss, and can minimize a space for disposing the inspection optical circuit. Provided is an inspection optical circuit for inspecting a tested circuit formed on an optical circuit chip on a wafer by inputting and outputting light through a grating coupler, wherein the grating coupler is formed on the same optical circuit chip as the tested circuit, and a folded waveguide for connecting an input/output waveguide of the tested circuit and the grating coupler is formed in a region provided on a dicing line for cutting out the optical circuit chip.

Claims (19)

1 . An inspection optical circuit for inspecting a tested circuit formed on an optical circuit chip on a wafer by inputting and outputting light through an optical path converter, wherein

the optical path converter is formed on the same optical circuit chip as the tested circuit, and

a folded waveguide for connecting an input/output waveguide of the tested circuit and the optical path converter is formed in a region provided on a dicing line for cutting out the optical circuit chip.

2 . The inspection optical circuit according to claim 1 , wherein the optical path converter is formed in a region to be polished and reduced by polishing after being cut off by dicing along the dicing line.

3 . The inspection optical circuit according to claim 1 , wherein the dicing line is a groove formed on the wafer, and the region is a region where the groove is not dug.

4 . The inspection optical circuit according to claim 1 , wherein the input/output waveguide of the tested circuit and the folded waveguide are connected via a spot-size converter including a tapered waveguide.

5 . The inspection optical circuit according to claim 1 , wherein the dicing line is a groove formed on the wafer, and the region is separated from the optical circuit chip by the groove.

6 . A method for manufacturing a plurality of optical circuit chips including a tested circuit on a wafer, the method comprising:

forming an optical path converter on the same optical circuit chip as the tested circuit;

forming a folded waveguide for connecting an input/output waveguide of the tested circuit and the optical path converter in a region provided on a dicing line for cutting out the optical circuit chip; and

removing the region by dicing along the dicing line after the tested circuit is inspected.

7 . The method according to claim 6 , wherein the optical path converter is formed in a region to be polished and reduced by polishing after being cut off by dicing along the dicing line.

8 . The method according to claim 6 , wherein the dicing line is a groove formed on the wafer, and the region is a region where the groove is not dug.

9 . The inspection optical circuit according to claim 2 , wherein the dicing line is a groove formed on the wafer, and the region is a region where the groove is not dug.

10 . The inspection optical circuit according to claim 2 , wherein the input/output waveguide of the tested circuit and the folded waveguide are connected via a spot-size converter including a tapered waveguide.

11 . The inspection optical circuit according to claim 3 , wherein the input/output waveguide of the tested circuit and the folded waveguide are connected via a spot-size converter including a tapered waveguide.

12 . The inspection optical circuit according to claim 9 , wherein the input/output waveguide of the tested circuit and the folded waveguide are connected via a spot-size converter including a tapered waveguide.

13 . The inspection optical circuit according to claim 2 , wherein the dicing line is a groove formed on the wafer, and the region is separated from the optical circuit chip by the groove.

14 . The method according to claim 7 , wherein the dicing line is a groove formed on the wafer, and the region is a region where the groove is not dug.

Assignments (2)
CHANGE OF NAME Recorded Aug 18, 2025
From: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
To: NTT, INC.
Reel/Frame 072507/0679 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 1, 2024
From: IKUMA, YUICHIRO; NASU, YUSUKE; KIKUCHI, KIYOFUMI; TAKAHASHI, MASAYUKI
To: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
Reel/Frame 066618/0355 →