DML DRIVER
An embodiment is a directly modulated laser (DML) driver, including a PMOS transistor having a source connected to a first power supply terminal and a drain connected to an anode of a laser diode, an NMOS transistor having a gate configured to be connected to an modulated input signal, and a source connected to a second power supply terminal, a resistor having one end connected to a first bias terminal, and the other end connected to the gate of the PMOS transistor, a first decoupling capacitor having one end connected to the first power supply terminal, and the other end connected to the second power supply terminal, and a plurality of decoupling capacitors each having one end connected to a respective bias terminal, and the other end connected to the first power supply terminal.
1 .- 4 . (canceled)
5 . A directly modulated laser (DML) driver comprising:
a first transistor having a source or emitter connected to a first power supply terminal, and a drain or collector configured to be connected to an anode of a laser diode;
a second transistor having a gate or base connected to an input signal terminal, a drain or collector configured to be connected to the anode of the laser diode, and a source or emitter connected to a second power supply terminal;
a first resistor having one end connected to a first bias terminal, and the other end connected to a gate or base of the first transistor;
a second resistor having one end connected to a second bias terminal, and the other end connected to a gate or base of the second transistor;
a first decoupling capacitor having one end connected to the first power supply terminal, and the other end connected to the second power supply terminal;
a second decoupling capacitor having one end connected to the first bias terminal, and the other end connected to the first power supply terminal;
a third decoupling capacitor having one end connected to the gate or base of the first transistor, and the other end connected to the first power supply terminal; and
a fourth decoupling capacitor having one end connected to the second bias terminal, and the other end connected to the first power supply terminal.
6 . The DML driver according to claim 5 , further comprising:
a third transistor cascode-connected between the anode of the laser diode and the drain or collector of the second transistor;
a third resistor having one end connected to a third bias terminal, and the other end connected to a gate or base of the third transistor;
a fifth decoupling capacitor having one end connected to the third bias terminal, and the other end connected to the first power supply terminal; and
a sixth decoupling capacitor having one end connected to the gate or base of the third transistor, and the other end connected to the first power supply terminal.
7 . The DML driver according to claim 5 , further comprising:
a fourth transistor cascode-connected between the drain or collector of the first transistor and the anode of the laser diode;
a fourth resistor having one end connected to a fourth bias terminal for applying a fourth bias voltage, and the other end connected to a gate or base of the fourth transistor;
a seventh decoupling capacitor having one end connected to the fourth bias terminal, and the other end connected to the first power supply terminal; and
an eighth decoupling capacitor having one end connected to the gate or base of the fourth transistor, and the other end connected to the first power supply terminal.
8 . The DML driver according to claim 5 , further comprising a fifth resistor inserted between the first power supply terminal and the source or emitter of the first transistor.
9 . The DML driver according to claim 6 , further comprising:
a fourth transistor cascode-connected between the drain or collector of the first transistor and the anode of the laser diode;
a fourth resistor having one end connected to a fourth bias terminal for applying a fourth bias voltage, and the other end connected to a gate or base of the fourth transistor;
a seventh decoupling capacitor having one end connected to the fourth bias terminal, and the other end connected to the first power supply terminal; and
an eighth decoupling capacitor having one end connected to the gate or base of the fourth transistor, and the other end connected to the first power supply terminal.
10 . The DML driver according to claim 6 , further comprising a fifth resistor inserted between the first power supply terminal and the source or emitter of the first transistor.
11 . The DML driver according to claim 7 , further comprising a fifth resistor inserted between the first power supply terminal and the source or emitter of the first transistor.
12 . A directly modulated laser (DML) driver, comprising:
a PMOS transistor having a source connected to a first power supply terminal and a drain connected to an anode of a laser diode;
an NMOS transistor having a gate configured to be connected to an modulated input signal, and a source connected to a second power supply terminal;
a resistor having one end connected to a first bias terminal, and the other end connected to the gate of the PMOS transistor;
a first decoupling capacitor having one end connected to the first power supply terminal, and the other end connected to the second power supply terminal; and
a plurality of decoupling capacitors each having one end connected to a respective bias terminal, and the other end connected to the first power supply terminal.
13 . The DML driver of claim 12 , wherein the PMOS transistor and the NMOS transistor are cascode-connected.
14 . The DML driver of claim 12 , wherein the resistor is an impedance matching resistor.
15 . The DML driver of claim 12 , wherein the DML driver is integrated within a driver integrated circuit for a laser diode array.
16 . A directly modulated laser (DML) driver system, comprising:
a plurality of DML drivers each having a PMOS transistor with a source connected to a first power supply terminal and a drain connected to an anode of a laser diode, an NMOS transistor with a gate to which a modulated signal is input, and a source connected to a second power supply terminal, a resistor having one end connected to a first bias terminal, and the other end connected to the gate of the PMOS transistor, a first decoupling capacitor having one end connected to the first power supply terminal, and the other end connected to the second power supply terminal, and a plurality of decoupling capacitors each having one end connected to a respective bias terminal, and the other end connected to the first power supply terminal;
wherein the DML drivers share the first power supply terminal, the second power supply terminal, the resistor, the first decoupling capacitor, and the plurality of decoupling capacitors.
17 . The DML driver system of claim 16 , wherein the PMOS transistor and the NMOS transistor are cascode-connected.