IP Library › Granted Patent US 12,524,533
Granted Patent B2
US 12,524,533 · App. 18/693,750 · Granted Jan 13, 2026

Consequence execution

Inventors: Russell Fredrickson (Vancouver, WA); Gary T. Brown (Boise, ID); John Harris (Boise, ID); Marvin Nelson (Boise, ID); Gary M. Nobel (San Diego, CA)
Assignee: Hewlett-Packard Development Company, L.P.
G06F21/554G06F21/567
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Quick Facts
Patent No.
US 12,524,533
App. No.
18/693,750
Granted
Jan 13, 2026
Kind
B2
Abstract

In some examples, a computing device can include a processing resource and hardware logic to cause the processing resource to receive input from a source indicating a security threat to a portion of a system in communication with the computing device, determine a consequence to address the security threat specific to the portion of the system and a function of the portion of the system, communicate the consequence to a secure processing resource, and determine whether to execute the consequence based on a response from the secure processing resource.

Claims (40)

1 . A computing device, comprising:

a processing resource; and

hardware logic to cause the processing resource to:

receive input from a source indicating a security threat to a portion of a system in communication with the computing device;

determine a consequence to address the security threat specific to the portion of the system and a function of the portion of the system;

communicate the consequence to a secure processing resource;

determine if the security threat should be ignored in response to the consequence being communicated to the secure processing resource; and

determine whether to execute the consequence based on a response from the secure processing resource.

2 . The computing device of claim 1 , further comprising the hardware logic to cause the processing resource to execute the consequence when the response is a non-response to the communication.

3 . The computing device of claim 1 , further comprising the hardware logic to cause the processing resource to:

execute the consequence when the response to the communication indicates execution of the consequence; and

do not execute the consequence when the response to the communication indicates avoidance of execution of the consequence.

4 . The computing device of claim 1 , wherein the consequence is a temporary disablement of a function of the portion of the system.

5 . The computing device of claim 1 , wherein the consequence is a reset of the portion of the system.

6 . The computing device of claim 1 , further comprising the hardware logic to cause the processing resource to receive the input as a one-time programmable (OTP) fuse configuration.

7 . The computing device of claim 1 , further comprising the hardware logic to cause the processing resource to receive the input via a direct-connected security monitor.

8 . The computing device of claim 1 , further comprising the hardware logic to cause the processing resource to receive the input via a firmware-initiated security action.

9 . A non-transitory machine-readable storage medium including instructions that when executed cause a processing resource of a computing device to:

detect a security threat to a portion of a system in communication with the computing device;

assert a first interrupt to alert the system and a secure processing resource of the system of the detection of the security threat;

in response to a threshold time period passing without a response from the system, the secure processing resource, or both, execute a consequence to address the security threat specific to the portion of the system and a function of the portion of the system;

in response to an affirmative consequence execution response within the threshold period of time from the system, the secure processing resource, or both, execute the consequence; and

in response to an avoid consequence execution response indicating the security threat should be ignored within the threshold period of time from the system, the secure processing resource, or both, do not execute the consequence.

10 . The medium of claim 9 , further comprising the instructions to cause the processing resource to:

execute the consequence by asserting a directly connected hardware signal to the portion of the system; and

assert a second interrupt in response to execution of the consequence to communicate execution of the consequence to the system and the secure processing resource.

11 . The medium of claim 10 , further comprising the instructions executable to accept interaction from the secure processing resource and reject interaction from other sources.

12 . The medium of claim 9 , wherein the consequence is a non-destructive consequence, and the instructions are further to cause the processing resource to:

cancel the consequence in response to receiving an indication that the security threat is over.

13 . A method, comprising:

detecting a security threat to a portion of a system in communication with a consequence device;

asserting a first interrupt to alert the system and a secure processing resource of the system of the detection of the security threat;

determining, by the consequence device, a consequence to address the security threat specific to the portion of the system and a function of the portion of the system;

determining, by the consequence device, that a response indicating the security threat should be ignored has not been received;

asserting a directly connected hardware signal to the portion of the system to execute the consequence; and

asserting a second interrupt in response to execution of the consequence to communicate execution of the consequence to the system and the secure processing resource.

14 . The method of claim 13 , wherein asserting the directly connected hardware signal to execute the consequence comprises asserting the directly connected hardware signal to reset the system, disable the portion of the system, or a combination thereof.

15 . The method of claim 13 , further comprising:

receiving an instruction from the secure processing resource to execute a particular consequence in response to asserting the first interrupt; and

asserting the directly connected hardware signal to the portion of the system to execute the particular consequence.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 29, 2024
From: FREDRICKSON, RUSSELL; BROWN, GARY T.; HARRIS, JOHN; NELSON, MARVIN; NOBEL, GARY M.
To: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Reel/Frame 067251/0147 →
Continuity (1)
Related Publication 20240386101A1 · Nov 21, 2024
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