Granted Patent B2

US 12,218,975 · App. 18/697,423 · Granted Feb 4, 2025

Inventors: Linge Xiao (Jiangsu, CN); Rui Hao (Jiangsu, CN); Hongwei Kan (Jiangsu, CN)

Assignee: SUZHOU METABRAIN INTELLIGENT TECHNOLOGY CO., LTD.

H04L63/166G06F13/4221G06F2213/0026

Abstract

Claims (57)

1. A method for processing a full-stack network card task based on Field-Programmable Gate Array (FPGA), the method comprising:

receiving to-be-processed data, and offloading a Transmission Control Protocol (TCP)/Internet Protocol (IP) task from the to-be-processed data by a built-in TCP offload engine, to obtain first processed data;

offloading an Secure Sockets Layer (SSL)/Transport Layer Security (TLS) protocol task from the first processed data, to obtain second processed data; and

acquiring, by a host, dynamic configuration information of a Partial Reconfiguration (PR) region where the second processed data is located, and configuring the PR region based on the dynamic configuration information, so that the PR region offloads and processes computation-intensive tasks in the second processed data;

wherein the PR region is a neural network model or an image inference model.

2. The method as claimed in claim 1 , wherein offloading the SSL/TLS protocol task from the first processed data, to obtain the second processed data, comprises:

receiving the first processed data, and distributing the first processed data to at least one idle SSL/TLS engine according to status signals fed back by SSL/TLS engines, as to execute SSL/TLS protocol task processing, and to generate at least one piece of second processed data; and

acquiring the at least one piece of second processed data from the at least one idle SSL/TLS engine and transferring the at least one piece of second processed data to the PR region.

3. The method as claimed in claim 2 , wherein distributing the first processed data to the at least one idle SSL/TLS engine according to status signals fed back by SSL/TLS engines, as to execute SSL/TLS protocol task processing, and to generate the at least one piece of second processed data, comprises:

writing at least one SSL/TLS engine serial number of at least one idle SSL/TLS engine executing the SSL/TLS protocol task processing at this time into an First Input First Output (FIFO) memory; and

reading the at least one SSL/TLS engine serial number from the FIFO memory, and acquiring the at least one piece of second processed data from at least one SSL/TLS engine corresponding to the at least one SSL/TLS engine serial number.

4. The method as claimed in claim 1 , wherein acquiring, by the host, the dynamic configuration information of the PR region where the second processed data is located, and configuring the PR region based on the dynamic configuration information, so that the PR region offloads and processes computation-intensive tasks in the second processed data, comprises:

acquiring the dynamic configuration information from a memory of the host, and storing the dynamic configuration information; and

taking out the dynamic configuration information and sending the dynamic configuration information to a PR Intellectual Property (IP) core, and sending out an interrupt signal after the sending is completed;

reconfiguring and programming the PR region based on the dynamic configuration information via a preset port by a fixed protocol; and

reading a preset register of the PR IP core to determine whether the reconfiguration is successful, and reporting a determination result to the host via a Peripheral Component Interconnect express (PCIe).

5. The method as claimed in claim 4 , wherein before reconfiguring and programming the PR region based on the dynamic configuration information via the preset port by the fixed protocol, the method further comprises:

checking whether the dynamic configuration information is correct; and

performing reconfiguration on the PR region in response to the dynamic configuration information is correct.

6. The method as claimed in claim 1 , wherein the FPGA communicates with the host via a PCIe bus.

7. A system for processing a full-stack network card task based on Field-Programmable Gate Array (FPGA), the system comprising:

a network interface controller, configured to receive to-be-processed data, and offload a Transmission Control Protocol (TCP)/Internet Protocol (IP) task from the to-be-processed data by a built-in TCP offload engine, to obtain first processed data;

an Secure Sockets Layer (SSL)/Transport Layer Security (TLS) protocol processing module, configured to receive the first processed data, and offload an SSL/TLS protocol task from the first processed data, to obtain second processed data;

a Partial Reconfiguration (PR) region, the PR region being configured to receive the second processed data; and

a reconfiguration module, configured to acquire, by a host, dynamic configuration information of the PR region, and configure the PR region based on the dynamic configuration information, so that the PR region offloads and processes computation-intensive tasks in the second processed data;

wherein the PR region is a neural network model or an image inference model.

8. The system as claimed in claim 7 , wherein the SSL/TLS protocol processing module comprises a first arbitration module, a second arbitration module and a plurality of SSL/TLS engines in parallel between the first arbitration module and the second arbitration module;

the first arbitration module, configured to receive the first processed data from the network interface controller, and distribute the first processed data to at least one idle SSL/TLS engine according to status signals fed back by SSL/TLS engines, as to execute SSL/TLS protocol task processing, and to generate at least one piece of second processed data; and

the second arbitration module, configured to acquire the at least one piece of second processed data from the at least one idle SSL/TLS engine and transfer the at least one piece of second processed data to the PR region.

9. The system as claimed in claim 8 , wherein the SSL/TLS protocol processing module further comprises a First Input First Output (FIFO) memory connected to both the first arbitration module and the second arbitration module;

the first arbitration module, configured to write at least one SSL/TLS engine serial number of at least one idle SSL/TLS engine executing the SSL/TLS protocol task processing at this time into the FIFO memory; and

the second arbitration module, configured to read the at least one SSL/TLS engine serial number from the FIFO memory, and acquire the at least one piece of second processed data from at least one SSL/TLS engine corresponding to the at least one SSL/TLS engine serial number.

10. The system as claimed in claim 7 , wherein the reconfiguration module comprises a PR Intellectual Property (IP) core, Double Date Rate (DDR), a Direct Memory Access (DMA) controller and a Checker;

the DMA controller, configured to acquire dynamic configuration information from a memory of the host according to a DMA descriptor sent by the host, and store the dynamic configuration information into the DDR; and

the DMA controller, configured to take out the dynamic configuration information from the DDR via a DDR controller and send the dynamic configuration information to the PR IP core, and send an interrupt signal to the Checker after the sending is completed;

the PR IP core, configured to reconfigure and program the PR region based on the dynamic configuration information via a preset port by a fixed protocol; and

the Checker, configured to read a preset register of the PR IP core to determine whether the reconfiguration is successful, and report a determination result to the host via a Peripheral Component Interconnect express (PCIe).

11. The system according to claim 10 , wherein the PR IP core comprises a Cyclic Redundancy Check (CRC) module and a PR control module;

the CRC module, configured to check whether the dynamic configuration information is correct; and

the PR control module, configured to perform reconfiguration on the PR region in response to the dynamic configuration information is correct.

12. The system according to claim 10 , wherein the PR IP core is further configured to freeze activities of all other signals except a global signal while executing the reconfiguration and programming.

13. The system as claimed in claim 10 , wherein the DMA controller and the PR IP core communicate via an Avalon bus.

14. The system as claimed in claim 10 , wherein the Checker and the PR IP core communicate via an Avalon bus.

15. The system as claimed in claim 7 , wherein the FPGA communicates with the host via a PCIe bus.

16. A computing processing device, comprising:

a memory in which computer-readable codes are stored;

and at least one processor, wherein when the computer-readable codes are executed by the at least one processor, the computing processing device executes following actions:

receive to-be-processed data, and offload a Transmission Control Protocol (TCP)/Internet Protocol (IP) task from the to-be-processed data by a built-in TCP offload engine, to obtain first processed data;

offload a Secure Sockets Layer (SSL)/Transport Layer Security (TLS) protocol task from the first processed data, to obtain second processed data; and

acquire, by a host, dynamic configuration information of a Partial Reconfiguration (PR) region where the second processed data is located, and configure the PR region based on the dynamic configuration information, so that the PR region offloads and processes computation-intensive tasks in the second processed data;

wherein the PR region is a neural network model or an image inference model.

17. The computing processing device according to claim 16 , wherein when the computer-readable codes are executed by the at least one processor, the computing processing device executes following actions:

receive the first processed data, and distributing the first processed data to at least one idle SSL/TLS engine according to status signals fed back by SSL/TLS engines, as to execute SSL/TLS protocol task processing, and to generate at least one piece of second processed data; and

acquire the at least one piece of second processed data from the at least one idle SSL/TLS engine and transferring the at least one piece of second processed data to the PR region.

18. The computing processing device according to claim 17 , wherein when the computer-readable codes are executed by the at least one processor, the computing processing device executes following actions:

write at least one SSL/TLS engine serial number of at least one idle SSL/TLS engine executing the SSL/TLS protocol task processing at this time into a First Input First Output (FIFO) memory; and

read the at least one SSL/TLS engine serial number from the FIFO memory, and acquiring the at least one piece of second processed data from at least one SSL/TLS engine corresponding to the at least one SSL/TLS engine serial number.

Assignments (2)

Priority Claims (1)

Continuity (1)

References Cited (19)