Method for characterizing in pulse mode a III-V semiconductor transistor and associated test bench
A method for characterizing in pulse-mode a III-V semiconductor transistor ( 2 ) utilizes an associated test bench ( 1 ). An RF pre-pulse is applied to the gate ( 2 a) of the transistor ( 2 ) with a power level NRF defined according to a first predetermined law of variation so as to fix the charge state of the traps in the transistor ( 2 ). Then a first DC pulse and a second DC pulse are applied to the gate ( 2 a) and to the drain ( 2 b) of the transistor ( 2 ), respectively. The first DC pulse and the second DC pulse have a first DC level N1 and a second DC level N2, respectively, defined according to a second predetermined law of variation.
1 . A method for characterizing in pulse mode a III-V semiconductor transistor ( 2 ), the transistor ( 2 ) comprising a gate ( 2 a ), a drain ( 2 b ) and a source ( 2 c ), characterized in that said method comprises the following steps:
a) defining (S 1 ; S 1 ′) a bias point of the transistor ( 2 ) corresponding to a bias gate-source voltage Vgs0 and to a bias drain-source voltage Vds0;
b) defining (S 3 ; S 1 ′) a load impedance ( 8 ) applied to the drain ( 2 b ) of the transistor ( 2 );
c) defining a period T, and for each period T:
c1) applying a radio frequency, RF, pre-pulse ( 9 ) to the gate ( 2 a ) of the transistor ( 2 ) so as to fix the charge state of the traps in the transistor ( 2 ), said RF pre-pulse ( 9 ) having a predefined frequency f0, a predefined pre-pulse duration TRF and a power level NRF defined according to a first predetermined law of variation;
c2) after the RF pre-pulse ( 9 ), applying a first DC pulse ( 10 ) to the gate ( 2 a ) of the transistor ( 2 ) and a second DC pulse ( 11 ) to the drain ( 2 b ) of the transistor ( 2 ), the first DC pulse ( 10 ) having a first duration T1 and the second DC pulse ( 11 ) having a second duration T2, the first and second durations T1, T2 being at least partially simultaneous, the first DC pulse ( 10 ) and the second DC pulse ( 11 ) having a first DC level N1 and a second DC level N2, respectively, defined according to a second predetermined law of variation; and
c3) during a measurement duration TM during the simultaneous application of the first and second DC pulses ( 10 , 11 ), measuring (S 6 ) the current Id flowing in the drain ( 2 b ) of the transistor ( 2 );
wherein, for each period T, in the first law of variation, the power level NRF of the RF pre-pulse ( 9 ) depends on the first N1 and second N2 DC levels of the first and second DC pulses ( 10 , 11 ) applied subsequently within the same period T;
wherein, for each period T, in the second law of variation, the first DC level N1 is equal to Vgs0 plus a first value V1 defined by the second law of variation according to the current period T, and the second DC level N2 is equal to Vds0 plus a second value V2 defined by the second law of variation according to the current period T, the first V1 and second V2 values being real numbers.
2 . The method for characterizing according to claim 1 , wherein the method further comprises, between steps a) and b), a step f determining (S 2 ) the period T and the durations TRF, T1 and T2 according to the measurement of the time constants of the traps in the transistor ( 2 ) on the gate ( 2 a ) and on the drain ( 2 b ) of the transistor ( 2 ).
3 . The method for characterizing according to claim 1 , wherein the method further comprises, between steps a) and b):
d1) defining (S 2 ) the lower and upper bounds [Vgsmin; Vgsmax] of the first DC level N1 in the second law of variation, where:
Vgsmax is determined by measuring the gate current Ig of the transistor ( 2 ) as a function of the DC voltage Vgs applied to the gate ( 2 a ) of the transistor ( 2 ) for a zero voltage Vds applied to the drain ( 2 b ) of the transistor ( 2 ), then by defining Vgsmax as the value of Vgs for which the gate current Ig reaches a predetermined current threshold value; and
Vgsmin≤Vp where Vp is the pinch-off voltage of the transistor ( 2 ); and
d2) defining (S 2 ) the lower and upper bounds [Vdsmin; Vdsmax] of the second DC level N2 in the second law of variation, where Vdsmin=0V and Vdsmax=2*Vds0.
4 . The method for characterizing according to claim 1 , wherein the method further comprises, between steps b) and c), a step of determining the first law of variation (S 4 ) comprising:
e1) for the defined load impedance ( 8 ) applied to the drain ( 2 b ) of the transistor ( 2 ), measuring the amplitude of Vgs over time at f0 or at a harmonic of f0 as a function of the power Pavs transmitted in an RF pulse at f0 or at a harmonic of f0, then defining different power levels Pavs1, . . . , Pavsn of the RF pulse by cutting the curve of variation of the measured amplitude of Vgs as a function of the power Pavs, each power level Pavs1, . . . , Pavsn corresponding to a certain range of the voltage Vgs;
e2) for the defined load impedance ( 8 ), measuring the curve of variation of the voltage Vgs as a function of the voltage Vds so as to determine possible pairs of values (N1, N2); and
e3) for each possible pair of values (N1, N2), determining the corresponding power level NRF to be applied to the RF pre-pulse ( 9 ) among the different power levels Pavs1, . . . , Pavsn.
5 . The method for characterizing according to claim 1 , wherein in step b) the load impedance ( 8 ) is defined (S 1 ′) by the user according to the final application, which defines (S 3 ′) a constraint on the compression level of the transistor ( 2 ).
6 . The method for characterizing according to claim 1 , wherein the step of defining the load impedance b) comprises:
measuring (S 31 ), at the bias point, the conjugate of the output reflection coefficient S22 of the transistor ( 2 ) at the frequency f0 and determining a corresponding initial load impedance;
performing (S 32 ) a measurement combining a power sweep with a variation of the load impedance around said initial load impedance in order to determine the optimum load impedance for which the excursion of voltage Vds is maximum for a minimum compression level; and
defining the load impedance ( 8 ) as being equal to the determined optimum load impedance.
7 . The method for characterizing according to claim 1 , wherein the method further comprises, between steps b) and c), a step of determining the second law of variation (S 5 ) comprising:
f1) for at least the first period T, defining V1=0 and V2=0; and
f2) for each of the following periods T, defining V1 and V2 in such a way that, over all periods T, N1 and N2 vary around the bias point while gradually moving away from the latter.
8 . The method for characterizing according to claim 1 , wherein the method further comprises, at each period T, the measurement of the S parameters on the gate ( 2 a ) and the drain ( 2 b ) of the transistor ( 2 ) during the application of the first and second DC pulses ( 10 , 11 ).
9 . The method for characterizing according to claim 1 , wherein step c3) further comprises: during the measurement duration TM, measuring the gate voltage, the drain voltage and the gate current of the transistor ( 2 ).
10 . A test bench ( 1 ) for characterizing in pulse mode a III-V semiconductor transistor ( 2 ), the test bench ( 1 ) comprising a pulsed RF generator ( 3 ), a first pulsed DC voltage source ( 4 ), a second pulsed DC voltage source ( 5 ), a first bias tee ( 6 ) and a second bias tee ( 7 ), the pulsed RF generator ( 3 ) and the first pulsed DC voltage source ( 4 ) being configured to be connected to the gate ( 2 a ) of the transistor ( 2 ) via the first bias tee ( 6 ), the second pulsed DC voltage source ( 5 ) and a load impedance ( 8 ) being configured to be connected to the drain ( 2 b ) of the transistor ( 2 ) via the second bias tee ( 7 ), the test bench ( 1 ) further comprising a controller configured to control the pulsed RF generator ( 3 ), the first pulsed DC voltage source ( 4 ) and the second pulsed DC voltage source ( 5 ) so as to carry out the method for characterizing according to claim 1 .
11 . The test bench ( 1 ) according to claim 10 , wherein the test bench ( 1 ) further comprises a vector network analyzer ( 12 ) configured to be connected to the gate ( 2 a ) and to the drain ( 2 b ) of the transistor ( 2 ) through couplers ( 13 , 14 ).