Communication link update method and apparatus, and related device
View Patent ↗Disclosed in the present application is a communication link update method. The method comprises: traversing registers in a target communication link, so as to determine a DownTrain register; setting a prohibition flag bit in the DownTrain register; reading configuration information of each register in the target communication link, so as to generate a configuration file; and updating each communication link by using the configuration file. By means of applying the technical solution provided in the present application, firstly, a DownTrain register is searched for in a target communication link, and then, a prohibition flag bit is set for the DownTrain register, such that in the case of partial Lane Down (shutdown) of the communication link, the entire link is shut down.
1. A communication link update method, comprising:
traversing registers in target communication links, so as to determine DownTrain registers;
setting a prohibition flag bit in each of the DownTrain registers to prohibit Down Train, such that communication links with partial Lane Down are shut down entirely;
reading configuration information of each register of the registers in the target communication links, so as to generate a configuration file; and
generating an upgrade task according to the configuration file, and sending the upgrade task to the communication links, whereby the communication links are updated according to the configuration file in the upgrade task.
2. The communication link update method according to claim 1 , wherein the traversing registers in the target communication links comprises:
traversing the registers in the target communication links by using a PLX_SDK toolkit.
3. The communication link update method according to claim 1 , wherein before the traversing registers in the target communication links, so as to determine the DownTrain registers, the communication link update method further comprises:
establishing a connection with the target communication links by using a Total Phase tool.
4. The communication link update method according to claim 3 , wherein the establishing the connection with the target communication links by using the Total Phase tool comprises:
establishing a connection with an inter-integrated circuit (I2C) interface of the target communication links by using the Total Phase tool.
5. The communication link update method according to claim 1 , wherein
each of the communication links of a same type as the target communication links is updated according to the configuration file in the upgrade task.
6. The communication link update method according to claim 5 , further comprising:
correspondingly configuring each register in each communication link of the communication links by using configuration information in the configuration file, and deleting original configuration information.
7. The communication link update method according to claim 1 , wherein the generating the upgrade task according to the configuration file, and sending the upgrade task to the communication links, whereby the communication links are updated according to the configuration file in the upgrade task comprises:
attaching the configuration file to an upgrade instruction, and issuing the upgrade instruction to each communication link of the communication links, whereby each communication link of the communication links obtains the configuration file through task analysis and is automatically updated based on the configuration file.
8. A communication link update device, comprising:
a memory, configured to store computer-readable instructions; and
one or more processors, upon execution of the computer-readable instructions, the one or more processors are configured for:
traversing registers in target communication links, so as to determine DownTrain registers;
setting a prohibition flag bit in each of the DownTrain registers to prohibit DownTrain, such that communication links with partial Lane Down are shut down entirely;
reading configuration information of each register of the registers in the target communication links, so as to generate a configuration file; and
generating an upgrade task according to the configuration file, and sending the upgrade task to the communication links, whereby the communication links are updated according to the configuration file in the upgrade task.
9. A non-volatile computer-readable storage medium, storing computer-readable instructions thereon, wherein when the computer-readable instructions are executed by one or more processors, the one or more processors are configured for:
traversing registers in target communication links, so as to determine DownTrain registers;
setting a prohibition flag bit in each of the DownTrain registers to prohibit Down Train, such that communication links with partial Lane Down are shut down entirely;
reading configuration information of each register of the registers in the target communication links, so as to generate a configuration file; and
generating an upgrade task according to the configuration file, and sending the upgrade task to the communication links, whereby the communication links are updated according to the configuration file in the upgrade task.
10. The communication link update method according to claim 1 , wherein the target communication links comprise peripheral component interconnect express (PCIe) communication links.
11. The communication link update method according to claim 1 , further comprising:
in response to the prohibition flag bit being set to 0, prohibiting the DownTrain registers, and in response to the prohibition flag bit being set to 1, allowing the DownTrain registers.
12. The communication link update method according to claim 1 , further comprising:
storing the configuration file into a corresponding storage space, and retrieving the configuration file from the corresponding storage space to update the communication links.
13. The communication link update device according to claim 8 , wherein upon execution of the computer-readable instructions, the one or more processors are further configured for:
traversing the registers in the target communication links by using a PLX_SDK toolkit, so as to determine the DownTrain registers.
14. The communication link update device according to claim 8 , wherein upon execution of the computer-readable instructions, the one or more processors are further configured for:
establishing a connection with the target communication links by using a Total Phase tool.
15. The communication link update device according to claim 14 , wherein upon execution of the computer-readable instructions, the one or more processors are further configured for:
establishing a connection with an inter-integrated circuit (I2C) interface of the target communication links by using the Total Phase tool.