Wireless power transfer
A power transmitter ( 101 ) provides power to a power receiver ( 105 ) via an inductive power transfer signal which is also used by the power receiver ( 105 ) for communication by load modulation. The power transmitter ( 101 ) comprises a load detector ( 209 ) detecting load variations for the power transfer signal and a preamble presence detector ( 213 ) correlates a second chip sequence with load variations and generates a preamble detection if the correlation exceeds a threshold. A load modulation receiver ( 207 ) determines load modulation data symbols based on a correlation of the first chip sequence and load variations of the power transfer signal. A synchronizer ( 215 ) synchronizes data symbol time intervals for the load modulation receiver ( 207 ) in response to a timing of the preamble detection, and the load modulation receiver ( 207 ) aligns the correlation of the first chip sequence and load variations to the data symbol time intervals. The power receiver ( 105 ) transmits the preamble and data symbols using the corresponding chip sequences.
1 . A device comprising:
an output circuit comprising:
a transmitter coil, wherein the transmitter coil is arranged to generate a power transfer signal in response to a drive signal;
a driver circuit, wherein the driver circuit is arranged to generate the drive signal; and
a load detector circuit, wherein the load detector circuit is arranged to detect a plurality of load variations of the power transfer signal;
a storage circuit,
wherein the storage circuit is arranged to store a first chip sequence and a second chip sequence,
wherein the first chip sequence has a first length,
wherein the second chip sequence has a second length,
wherein the second length is greater than the first length;
a preamble presence detector circuit,
wherein the preamble presence detector circuit is arranged to correlate the second chip sequence with the plurality of load variations of the power transfer signal so as to generate detection of a plurality of correlation values,
wherein the preamble presence detector circuit is arranged to detect a preamble in response to a detection correlation value exceeding a preamble detection threshold;
a load modulation receiver circuit, wherein the load modulation receiver circuit is arranged to determine load modulation data symbols following the detection of the preamble based on a correlation of the first chip sequence and the plurality of load variations of the power transfer signal;
a synchronizer circuit,
wherein the synchronizer circuit is arranged to synchronize a plurality of data symbol time intervals for the load modulation receiver circuit in response to a timing of the detection of the preamble,
wherein the load modulation receiver circuit is arranged to align the correlation of the first chip sequence and the plurality of load variations of the power transfer signal to the plurality of data symbol time intervals.
2 . The apparatus of claim 1 ,
wherein the synchronizer circuit is arranged to determine the plurality of data symbol time intervals as repeating time intervals,
wherein the repeating time intervals have a duration equal to a duration of the first chip sequence,
wherein the repeating time intervals have a predetermined time offset to the detection of a preamble.
3 . The apparatus of claim 1 , wherein the second length no less than twice the first length.
4 . The apparatus of claim 1 ,
wherein the first chip sequence has a first chip rate,
wherein the second chip sequence has a second chip rate,
wherein the first chip rate is greater than the second chip rate.
5 . The apparatus of claim 1 ,
wherein the first chip sequence has a first chip rate,
wherein the second chip sequence has a second chip rate,
wherein the first chip rate is smaller than the second chip rate.
6 . The apparatus of claim 1 ,
wherein the plurality of correlation values comprises a first correlation value,
wherein the load modulation receiver circuit is arranged to determine a first received data symbol value if the first correlation value in a first data symbol time interval exceeds a data symbol threshold,
wherein the data symbol threshold is lower than the preamble detection threshold.
7 . The apparatus of claim 1 , wherein the modulation receiver is arranged to determine binary data symbol values corresponding to a sign of the correlation of the first chip sequence and the plurality of load variations of the power transfer signal in the plurality of data symbol time intervals.
8 . The apparatus of claim 1 ,
wherein the preamble presence detector circuit is arranged to correlate the plurality of load variations of the power transfer signal with a third chip sequence,
wherein the third chip sequence is a portion of the second chip sequence,
wherein the preamble presence detector circuit is arranged to initiate a correlation of the power transfer signal with the second chip sequence in response to a detection that a correlation value for the correlation between the plurality of load variations of the power transfer signal with a third chip sequence exceeds a detection threshold.
9 . The apparatus of claim 8 ,
wherein the third chip sequence is a portion of the second chip sequence having an autocorrelation higher than any autocorrelation of any chip sequence of contiguous chips of the second chip sequence with a length equal to a length of third chip sequence.
10 . The apparatus of claim 1 , wherein the preamble presence detector circuit is arranged to synchronize the second chip sequence to the drive signal when correlating the second chip sequence with the plurality of load variations of the power transfer signal.
11 . The apparatus of claim 1 ,
wherein the preamble presence detector circuit is arranged to generate a noise estimate for the power transfer signal,
wherein the preamble presence detector circuit is arranged to adapt the preamble detection threshold in response to the noise estimate.