X-masking for in-system deterministic test
A circuit comprises: scan chains comprising scan cells, the scan chains configured to shift in test patterns, apply the test patterns to the circuit, capture test responses of the circuit, and shift out the test responses; a decompressor configured to decompress compressed test patterns into the test patterns; and a test response compactor configured to compact the test responses, the test response compactor comprising: first X-masking circuitry configured to mask, based on first masking information, some of X bits in the test responses, the first masking information remaining the same while a test response for each of the test patterns is being shifted out, the first masking information being different for at least two of the test patterns; and second masking circuitry configured to mask, based on second masking information, rest of the X bits in the test responses.
1 . A circuit, comprising:
scan chains comprising scan cells, the scan chains configured to shift in test patterns, apply the test patterns to the circuit, capture test responses of the circuit, and shift out the test responses;
a decompressor configured to decompress compressed test patterns into the test patterns; and
a test response compactor configured to compact the test responses, the test response compactor comprising:
first X-masking circuitry configured to mask, based on first masking information, some of X bits in the test responses, the first masking information remaining the same while a test response for each of the test patterns is being shifted out, the first masking information being different for at least two of the test patterns, wherein the first X-masking circuitry operates in a per test pattern mode; and
second X-masking circuitry configured to mask, based on second masking information, rest of the X bits in the test responses, wherein the second X-masking circuitry operates in a per clock cycle mode and comprises
decompressing circuitry configured to generate a gating control signal from a compressed mask signal, the decompressing circuitry comprising a hold register configured to keep outputs of the decompressing circuitry from changing for some clock cycles based on a hold signal, and
gating circuitry configured to gate signals at inputs of the gating circuitry based on the outputs of the decompressing circuitry.
2 . The circuit recited in claim 1 , wherein the first X-masking circuitry is configured to block outputs from some of the scan chains based on the first masking information.
3 . The circuit recited in claim 1 , wherein the test response compactor further comprises:
spatial test response compacting circuitry with inputs coupled to outputs of the first X-masking circuitry.
4 . The circuit recited in claim 1 , wherein the test response compactor further comprises:
a multiple input signature register with inputs coupled to outputs of the second X-masking circuitry or sticky-bits circuitry with inputs coupled to outputs of the second X-masking circuitry.
5 . The circuit recited in claim 1 , wherein the second X-masking circuitry further comprises:
an enable register configured to store enable data; and
another gating circuitry configured to generate an enabled gating control signal by gating the gating control signal based on the enable data,
wherein the gating circuitry configured to gate signals at inputs of the gating circuitry based on the enabled gating control signal.
6 . The circuit recited in claim 5 , wherein the decompressing circuitry further comprises a decompressing unit, the decompressing unit being a standalone device or a part of the decompressor.
7 . The circuit recited in claim 1 , wherein the decompressing circuitry comprises a decompressing unit, the decompressing unit being a standalone device or a part of the decompressor.
8 . One or more non-transitory computer-readable media storing computer-executable instructions for causing a computer to perform a method, the method comprising:
creating a circuit in a circuit design for testing a chip fabricated according to the circuit design, the circuit comprising:
scan chains comprising scan cells, the scan chains configured to shift in test patterns, apply the test patterns to the circuit, capture test responses of the circuit, and shift out the test responses;
a decompressor configured to decompress compressed test patterns into the test patterns; and
a test response compactor configured to compact the test responses, the test response compactor comprising:
first X-masking circuitry configured to mask, based on first masking information, some of X bits in the test responses, the first masking information remaining the same while a test response for each of the test patterns is being shifted out, the first masking information being different for at least two of the test patterns, wherein the first X-masking circuitry operates in a per test pattern mode; and
second X-masking circuitry configured to mask, based on second masking information, rest of the X bits in the test responses, wherein the second X-masking circuitry operates in a per clock cycle mode and comprises
decompressing circuitry configured to generate a gating control signal from a compressed mask signal, the decompressing circuitry comprising a hold register configured to keep outputs of the decompressing circuitry from changing for some clock cycles based on a hold signal, and
gating circuitry configured to gate signals at inputs of the gating circuitry based on the outputs of the decompressing circuitry.
9 . The one or more non-transitory computer-readable media recited in claim 8 , wherein the first X-masking circuitry is configured to block outputs from some of the scan chains based on the first masking information.
10 . The one or more non-transitory computer-readable media recited in claim 8 , wherein the test response compactor further comprises:
spatial test response compacting circuitry with inputs coupled to outputs of the first X-masking circuitry.
11 . The one or more non-transitory computer-readable media recited in claim 8 , wherein the test response compactor further comprises:
a multiple input signature register with inputs coupled to outputs of the second X-masking circuitry or sticky-bits circuitry with inputs coupled to outputs of the second X-masking circuitry.
12 . The one or more non-transitory computer-readable media recited in claim 8 , wherein the second X-masking circuitry further comprises:
an enable register configured to store enable data; and
another gating circuitry configured to generate an enabled gating control signal by gating the gating control signal based on the enable data,
wherein the gating circuitry configured to gate signals at inputs of the gating circuitry based on the enabled gating control signal.
13 . The one or more non-transitory computer-readable media recited in claim 12 , wherein the decompressing circuitry further comprises a decompressing unit, the decompressing unit being a standalone device or a part of the decompressor.
14 . The one or more non-transitory computer-readable media recited in claim 8 , wherein the decompressing circuitry comprises a decompressing unit, the decompressing unit being a standalone device or a part of the decompressor.