IP Library › Patent Application 18718692
Patent Application
App. No. 18/718,692

PHASE ADJUSTMENT CIRCUIT

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Quick Facts
Patent No.
US None
App. No.
18/718,692
Abstract

In some implementations, the device may include a clock generator configured to generate a sinusoidal clock signal. The device may include a delay circuit configured to delay a signal output from the clock generator. The device may also include a first multiplier configured to output a signal obtained by multiplying an amplitude of the signal output from the clock generator by a first constant. Additionally, the device may include a second multiplier configured to output a signal obtained by multiplying an amplitude of the signal output from the delay circuit by a second constant. Also, the device may include an adder configured to add the signal output from the first multiplier and the signal output from the second multiplier.

Claims (113)

1 - 6 . (canceled)

7 . A phase adjustment circuit comprising:

a clock generator configured to generate a sinusoidal clock signal;

a delay circuit configured to delay a signal output from the clock generator;

a first multiplier configured to output a signal obtained by multiplying an amplitude of the signal output from the clock generator by a first constant;

a second multiplier configured to output a signal obtained by multiplying an amplitude of the signal output from the delay circuit by a second constant; and

an adder configured to add the signal output from the first multiplier and the signal output from the second multiplier.

8 . The phase adjustment circuit according to claim 7 , wherein the first multiplier includes:

a first transistor including a base or a gate to which a first control signal or a signal of a negative phase side of the clock signal of a differential type is input, and a collector or a drain from which a signal of a positive phase side is output;

a second transistor including a base or a gate to which a second control signal or a signal of a positive phase side of the clock signal of the differential type is input, and a collector or a drain from which a signal of a negative phase side is output;

a third transistor including a base or a gate to which the first control signal or the signal of the negative phase side of the clock signal of the differential type is input, and a collector or a drain from which the signal of the negative phase side is output;

a fourth transistor including a base or a gate to which the second control signal or the signal of the positive phase side of the clock signal of the differential type is input, and a collector or a drain from which the signal of the positive phase side is output;

a fifth transistor including a base or a gate to which the signal of the positive phase side of the clock signal of the differential type or the second control signal is input, and a collector or a drain connected to an emitter or a source of the first transistor and an emitter or a source of the second transistor;

a sixth transistor including a base or a gate to which one of the signal of the negative phase side of the clock signal of the differential type and the first control signal is input, and a collector or a drain connected to an emitter or a source of the third transistor and an emitter or a source of the fourth transistor;

a seventh transistor including a base or a gate to which a bias voltage is applied;

a first resistor including one end connected to a power supply voltage, and another end connected to a collector or a drain of the first transistor and a collector or a drain of the fourth transistor;

a second resistor including one end connected to the power supply voltage, and another end connected to a collector or a drain of the second transistor and a collector or a drain of the third transistor;

a third resistor including one end connected to an emitter or a source of the fifth transistor, and another end connected to a collector or a drain of the seventh transistor;

a fourth resistor including one end connected to an emitter or a source of the sixth transistor, and another end connected to the collector or the drain of the seventh transistor; and

a fifth resistor including one end connected to an emitter or a source of the seventh transistor, and another end connected to ground; and

wherein the second multiplier includes:

an eighth transistor including a base or a gate to which one of a third control signal and a signal of a negative phase side of a differential signal output from the delay circuit is input, and a collector or a drain from which a signal of a positive phase is output;

a ninth transistor including a base or a gate to which one of a fourth control signal and a signal of a positive phase side of the differential signal output from the delay circuit is input, and a collector or a drain from which a signal of a negative phase is output;

a tenth transistor including a base or a gate to which one of the third control signal and the signal of the negative phase side of the differential signal output from the delay circuit is input, and a collector or a drain from which the signal of the negative phase side is output;

an eleventh transistor including a base or a gate to which one of the fourth control signal and the signal of the positive phase side of the differential signal output from the delay circuit is input, and a collector or a drain from which the signal of the positive phase is output;

a twelfth transistor including a base or a gate to which one of the signal of the positive phase side of the differential signal output from the delay circuit and the fourth control signal is input, and a collector or a drain connected to an emitter or a source of the eighth transistor and an emitter or a source of the ninth transistor;

a thirteenth transistor including a base or a gate to which one of the signal of the negative phase side of the differential signal output from the delay circuit and the third control signal is input, and a collector or a drain connected to an emitter or a source of the tenth transistor and an emitter or a source of the eleventh transistor;

a fourteenth transistor including a base or a gate to which a bias voltage is applied;

a sixth resistor including one end connected to the power supply voltage, and another end connected to a collector or a drain of the eighth transistor and a collector or a drain of the eleventh transistor;

a seventh resistor including one end connected to the power supply voltage, and another end connected to a collector or a drain of the ninth transistor and a collector or a drain of the tenth transistor;

an eighth resistor including one end connected to an emitter or a source of the twelfth transistor, and another end connected to a collector or a drain of the fourteenth transistor;

a ninth resistor including one end connected to an emitter or a source of the thirteenth transistor, and another end connected to the collector or the drain of the fourteenth transistor; and

a tenth resistor including one end connected to an emitter or a source of the fourteenth transistor, and another end connected to ground.

9 . The phase adjustment circuit according to claim 8 , wherein the adder includes:

a fifteenth transistor including a base or a gate to which the signal of the negative phase side of the differential signal output from the first multiplier is input, and a collector or a drain from which the signal of the positive phase side is output;

a sixteenth transistor including a base or a gate to which the signal of the positive phase side of the differential signal output from the first multiplier is input, and a collector or a drain from which the signal of the negative phase side is output;

a seventeenth transistor including a base or a gate to which the signal of the positive phase side of the differential signal output from the second multiplier is input, and a collector or a drain from which the signal of the negative phase side is output;

an eighteenth transistor including a base or a gate to which the signal of the negative phase side of the differential signal output from the second multiplier is input, and a collector or a drain from which the signal of the positive phase side is output;

a nineteenth transistor and a twentieth transistor, each including a base or a gate to which a bias voltage is applied;

an eleventh resistor including one end connected to the power supply voltage, and another end connected to a collector or a drain of the fifteenth transistor and a collector or a drain of the eighteenth transistor;

a twelfth resistor including one end connected to the power supply voltage, and another end connected to a collector or a drain of the sixteenth transistor and a collector or a drain of the seventeenth transistor;

a thirteenth resistor including one end connected to an emitter or a source of the fifteenth transistor, and another end connected to a collector or a drain of the nineteenth transistor;

a fourteenth resistor including one end connected to an emitter or a source of the sixteenth transistor, and another end connected to the collector or the drain of the nineteenth transistor;

a fifteenth resistor including one end connected to an emitter or a source of the seventeenth transistor, and another end connected to a collector or a drain of the twentieth transistor;

a sixteenth resistor including one end connected to an emitter or a source of the eighteenth transistor, and another end connected to the collector or the drain of the twentieth transistor;

a seventeenth resistor including one end connected to an emitter or a source of the nineteenth transistor, and another end connected to ground; and

an eighteenth resistor including one end connected to an emitter or a source of the twentieth transistor, and another end connected to ground.

10 . The phase adjustment circuit according to claim 8 , wherein the delay circuit includes:

a plurality of delay circuits with different delay amounts; and

a switch inserted between the plurality of delay circuits and the second multiplier and configured to select any one output of the plurality of delay circuits.

11 . The phase adjustment circuit according to claim 8 , further comprising:

a level adjusting circuit configured to perform an amplitude adjustment of the signal output from the adder.

12 . The phase adjustment circuit according to claim 7 , wherein the adder includes:

a fifteenth transistor including a base or a gate to which a signal of a negative phase side of a differential signal output from the first multiplier is input, and a collector or a drain from which a signal of a positive phase side is output;

a sixteenth transistor including a base or a gate to which a signal of a positive phase side of the differential signal output from the first multiplier is input, and a collector or a drain from which a signal of a negative phase side is output;

a seventeenth transistor including a base or a gate to which a signal of a positive phase side of a differential signal output from the second multiplier is input, and a collector or a drain from which the signal of the negative phase side is output;

an eighteenth transistor including a base or a gate to which a signal of a negative phase side of the differential signal output from the second multiplier is input, and a collector or a drain from which the signal of the positive phase side is output;

a nineteenth transistor and a twentieth transistor, each including a base or a gate to which a bias voltage is applied;

an eleventh resistor including one end connected to a power supply voltage, and another end connected to a collector or a drain of the fifteenth transistor and a collector or a drain of the eighteenth transistor;

a twelfth resistor including one end connected to the power supply voltage, and another end connected to a collector or a drain of the sixteenth transistor and a collector or a drain of the seventeenth transistor;

a thirteenth resistor including one end connected to an emitter or a source of the fifteenth transistor, and another end connected to a collector or a drain of the nineteenth transistor;

a fourteenth resistor including one end connected to an emitter or a source of the sixteenth transistor, and another end connected to the collector or the drain of the nineteenth transistor;

a fifteenth resistor including one end connected to an emitter or a source of the seventeenth transistor, and another end connected to a collector or a drain of the twentieth transistor;

a sixteenth resistor including one end connected to an emitter or a source of the eighteenth transistor, and another end connected to the collector or the drain of the twentieth transistor;

a seventeenth resistor including one end connected to an emitter or a source of the nineteenth transistor, and another end connected to ground; and

an eighteenth resistor including one end connected to an emitter or a source of the twentieth transistor, and another end connected to ground.

13 . The phase adjustment circuit according to claim 12 , wherein the delay circuit includes:

a plurality of delay circuits with different delay amounts; and

a switch inserted between the plurality of delay circuits and the second multiplier and configured to select any one output of the plurality of delay circuits.

14 . The phase adjustment circuit according to claim 12 , further comprising:

a level adjusting circuit configured to perform an amplitude adjustment of the signal output from the adder.

15 . The phase adjustment circuit according to claim 7 , wherein the delay circuit includes:

a plurality of delay circuits with different delay amounts; and

a switch inserted between the plurality of delay circuits and the second multiplier and configured to select any one output of the plurality of delay circuits.

16 . The phase adjustment circuit according to claim 15 , further comprising:

a level adjusting circuit configured to perform an amplitude adjustment of the signal output from the adder.

17 . The phase adjustment circuit according to claim 7 , further comprising:

a level adjusting circuit configured to perform an amplitude adjustment of the signal output from the adder.

18 . A phase adjustment circuit comprising:

a clock generator configured to generate a sinusoidal clock signal;

a delay circuit configured to delay a signal output from the clock generator; and

a process circuit including:

a first multiplier configured to output a signal obtained by multiplying an amplitude of the signal output from the clock generator by a first constant;

a second multiplier configured to output a signal obtained by multiplying an amplitude of the signal output from the delay circuit by a second constant; and

an adder configured to add the signal output from the first multiplier and the signal output from the second multiplier,

wherein the process circuit includes:

a first transistor including a base or a gate to which one of a first control signal and a signal of a negative phase side of the clock signal of a differential type is input, and a collector or a drain from which a signal of a positive phase side is output;

a second transistor including a base or a gate to which one of a second control signal and a signal of a positive phase side of the clock signal of the differential type is input, and a collector or a drain from which a signal of a negative phase side is output;

a third transistor including a base or a gate to which one of the first control signal and the signal of the negative phase side of the clock signal of the differential type is input, and a collector or a drain from which the signal of the negative phase side is output;

a fourth transistor including a base or a gate to which one of the second control signal and the signal of the positive phase side of the clock signal of the differential type is input, and a collector or a drain from which the signal of the positive phase side is output;

a fifth transistor including a base or a gate to which one of the signal of the positive phase side of the clock signal of the differential type and the second control signal is input, and a collector or a drain connected to an emitter or a source of the first transistor and an emitter or a source of the second transistor;

a sixth transistor including a base or a gate to which one of the signal of the negative phase side of the clock signal of the differential type and the first control signal is input, and a collector or a drain connected to an emitter or a source of the third transistor and an emitter or a source of the fourth transistor;

a seventh transistor including a base or a gate to which a bias voltage is applied;

an eighth transistor including a base or a gate to which one of a third control signal and a signal of a negative phase side of a differential signal output from the delay circuit is input, and a collector or a drain from which a signal of a positive phase side is output;

a ninth transistor including a base or a gate to which one of a fourth control signal and a signal of a positive phase side of the differential signal output from the delay circuit is input, and a collector or a drain from which a signal of a negative phase side is output;

a tenth transistor including a base or a gate to which one of the third control signal and the signal of the negative phase side of the differential signal output from the delay circuit is input, and a collector or a drain from which the signal of the negative phase side is output;

an eleventh transistor including a base or a gate to which one of the fourth control signal and the signal of the positive phase side of the differential signal output from the delay circuit is input, and a collector or a drain from which the signal of the positive phase side is output;

a twelfth transistor including a base or a gate to which one of the signal of the positive phase side of the differential signal output from the delay circuit and the fourth control signal is input, and a collector or a drain connected to an emitter or a source of the eighth transistor and an emitter or a source of the ninth transistor;

a thirteenth transistor including a base or a gate to which one of the signal of the negative phase side of the differential signal output from the delay circuit and the third control signal is input, and a collector or a drain connected to an emitter or a source of the tenth transistor and an emitter or a source of the eleventh transistor;

a fourteenth transistor including a base or a gate to which a bias voltage is applied;

a first resistor including one end connected to a power supply voltage, and another end connected to a collector or a drain of the first transistor, a collector or a drain of the fourth transistor, a collector or a drain of the eighth transistor and a collector or a drain of the eleventh transistor;

a second resistor including one end connected to the power supply voltage, and another end connected to a collector or a drain of the second transistor, a collector or a drain of the third transistor, a collector or a drain of the ninth transistor and a collector or a drain of the tenth transistor;

a third resistor including one end connected to an emitter or a source of the fifth transistor, and another end connected to a collector or a drain of the seventh transistor;

a fourth resistor including one end connected to an emitter or a source of the sixth transistor, and another end connected to the collector or the drain of the seventh transistor;

a fifth resistor including one end connected to an emitter or a source of the seventh transistor, and another end connected to ground;

a sixth resistor including one end connected to an emitter or a source of the twelfth transistor, and another end connected to a collector or a drain of the fourteenth transistor;

a seventh resistor including one end connected to an emitter or a source of the thirteenth transistor, and another end connected to the collector or the drain of the fourteenth transistor; and

an eighth resistor including one end connected to an emitter or a source of the fourteenth transistor, and another end connected to ground.

19 . The phase adjustment circuit according to claim 18 , wherein the delay circuit includes:

a plurality of delay circuits with different delay amounts; and

a switch inserted between the plurality of delay circuits and the second multiplier and configured to select any one output of the plurality of delay circuits.

20 . The phase adjustment circuit according to claim 18 , further comprising:

a level adjusting circuit configured to perform an amplitude adjustment of the signal output from the adder.

Assignments (1)
CHANGE OF NAME Recorded Oct 7, 2025
From: NIPPON TELEGRAPH AN D TELEPHONE CORPORATION
To: NTT, INC.
Reel/Frame 073014/0979 →