Granted Patent B2

US 12,700,989 · App. 18/719,495 · Granted Aug 4, 2026

Inventors: Shaveer Bajpeyi (Toronto, CA); Glenn Gulak (Etobicoke, CA)

Assignee: THE GOVERNING COUNCIL OF THE UNIVERSITY OF TORONTO

H04L9/008H04L9/0618

Abstract

Claims (52)

1 . A cryptographic processor, comprising:

a first cryptographic processing module to perform a first logic operation, the first cryptographic processing module including:

first input circuitry to receive ciphertext input symbols;

a first pipeline stage to perform a first operation on the ciphertext input symbols and to generate a first stage output;

storage circuitry to store constants for use by the first pipeline stage, the storage circuitry including an input interface configured with a bit-width to receive at least one entire ciphertext or key coefficient per cycle of a system clock, the storage circuitry configured to temporarily store the first stage output and to feed a second pipeline stage in a pipelined manner; and

wherein the second pipeline stage is configured to perform a second operation on the first stage output in a pipelined manner with respect to the first pipeline stage.

2 . The cryptographic processor of claim 1 , wherein:

the first input circuitry receives the ciphertext input symbols synchronous with an instruction clock signal; and

wherein a new set of input ciphertext symbols are presented to the first input circuitry each cycle of the instruction clock signal.

3 . The cryptographic processor of claim 1 , wherein:

the first cryptographic processing module is configured to perform ciphertext multiplication operations, ciphertext rotation operations, or ciphertext addition operations.

4 . The cryptographic processor of claim 1 , further comprising:

at least one Chinese Remainder Theorem (CRT) processing stage.

5 . The cryptographic processor of claim 4 , wherein:

the first cryptographic processing module is configured as a Residue Number System (RNS) architecture.

6 . The cryptographic processor of claim 5 , wherein:

the first cryptographic processing module includes multiple processing slices defining multiple processing channels, each channel to perform operations on signals 64-bits wide or less concurrently with the other processing channels.

7 . The cryptographic processor of claim 1 , wherein:

the first cryptographic processing module is configured as a Large Arithmetic Word Size (LAWS) architecture.

8 . The cryptographic processor of claim 7 , wherein:

the first cryptographic processing module includes a single processing slice defining a single processing channel to perform operations on signals that are more than 64-bits wide.

9 . The cryptographic processor of claim 1 , further comprising:

a second processing module to perform a second logic operation different than the first logic operation.

10 . The cryptographic processor of claim 1 , wherein the storage circuitry includes:

on-chip register circuitry configured to temporarily store the input of each stage.

11 . The cryptographic processor of claim 1 , wherein:

the first cryptographic processing module produces outputs with a pre-determined latency of execution cycles and constant throughput.

12 . The cryptographic processor of claim 1 , wherein:

the first pipeline stage comprises a stage of number theoretic transform (NTT) circuits to perform an NTT operation as the first operation, the stage of NTT circuits configured to exhibit a predetermined parallelism; and

wherein the second pipeline stage is configured to employ a number of inputs and outputs that match the predetermined parallelism of the stage of NTT circuits.

13 . A cryptographic processor, comprising:

a first cryptographic processing module including:

first input circuitry to receive ciphertext input symbols;

a number theoretic transform (NTT) stage to perform an NTT operation on received ciphertext input symbols and to generate an NTT stage output, the NTT stage configured to exhibit a predetermined parallelism;

a second circuit stage that receives the NTT stage output in a pipelined manner; and

wherein the second circuit stage is configured to employ a number of inputs and outputs that matches the predetermined parallelism of the NTT circuit.

14 . The cryptographic processor of claim 13 , wherein:

the first input circuitry receives the ciphertext input symbols synchronous with an instruction clock signal; and

wherein a new set of input ciphertext symbols are presented to the first input circuitry each cycle of the instruction clock signal.

15 . The cryptographic processor of claim 13 , wherein:

the first cryptographic processing module is configured to perform ciphertext addition operations or ciphertext multiplication operations or ciphertext rotation operations.

16 . The cryptographic processor of claim 13 , wherein:

the first cryptographic processing module is configured as a Residue Number System (RNS) architecture and includes multiple processing slices defining multiple processing channels, each channel to perform operations on signals 64-bits wide or less concurrently with the other processing channels.

17 . The cryptographic processor of claim 13 , wherein:

the first cryptographic processing module is configured as a Large Arithmetic Word Size (LAWS) architecture and includes a single processing slice defining a single processing channel to perform operations on signals that are more than 64-bits wide.

18 . The cryptographic processor of claim 13 , wherein:

the first cryptographic processing module produces outputs with a pre-determined latency of execution cycles and constant throughput.

19 . A method of operation in a cryptographic processor, the method comprising:

receiving ciphertext input symbols with first input circuitry;

performing a number theoretic transform (NTT) operation on the received ciphertext input symbols with an NTT stage and generating an NTT stage output, the NTT stage configured to exhibit a predetermined parallelism;

receiving the NTT stage output in a pipelined manner with a second pipeline stage; and

configuring the second pipeline stage to employ a number of inputs and outputs that matches the predetermined parallelism of the NTT circuit.

Assignments (1)

Continuity (3)

References Cited (109)