Solid-state imaging device with ramp generator circuit
Pixel circuits of a solid-state imaging device are arranged in pixel columns, wherein, for each pixel column, signal outputs of the pixel circuits are connected to a data signal line. The solid-state imaging device further includes comparator circuits, wherein each comparator circuit generates an active comparator signal in response to a voltage difference between a first comparator input and a second comparator input. Each first comparator input is connected to one of the data signal lines. A ramp generator circuit includes at least one resistor network and buffer circuits. The ramp generator circuit generates a voltage ramp signal based on voltages at voltage tap nodes of the at least one resistor network. Each buffer circuit passes a buffered voltage ramp signal to the second comparator input of at least one of the comparator circuits.
1 . A solid-state imaging device, comprising:
pixel circuits arranged in pixel columns, wherein for each pixel column, signal outputs of the pixel circuits are connected to a data signal line;
comparator circuits, wherein each comparator circuit is configured to generate an active comparator signal in response to a voltage difference between a first comparator input and a second comparator input, and wherein each first comparator input is connected to one of the data signal lines; and
a ramp generator circuit including at least one resistor network and buffer circuits, wherein the ramp generator circuit is configured to generate a voltage ramp signal based on voltages at voltage tap nodes of the at least one resistor network, wherein
the ramp generator circuit includes a first circuit and a plurality of second resistor circuits,
the first circuit is configured to generate at least one internal voltage signal,
each second circuit is configured to generate one of the buffered voltage ramp signals in response to the internal voltage signal, and
each buffer circuit is configured to pass a buffered voltage ramp signal to the second comparator input of at least one of the comparator circuits.
2 . The solid-state imaging device according to claim 1 , further comprising:
switch matrix circuits, wherein each switch matrix circuit includes electronic switches, and wherein each electronic switch is operable to connect one of the voltage tap nodes of the at least one resistor network with an input of one of the buffer circuits.
3 . The solid-state imaging device according to claim 2 , further comprising:
a ramp control circuit configured to control the electronic switches, wherein the ramp control circuit is configured to change a switching rate of the electronic switches at slope transition points.
4 . The solid-state imaging device according to claim 1 , further comprising:
a reference voltage circuit configured to supply a reference voltage to a voltage tap node of at least one of the resistor networks.
5 . The solid-state imaging device according to claim 1 , wherein the ramp generator circuit includes one resistor network, and wherein the ramp generator circuit is configured to switch the voltage tap nodes of the resistor network to the input of each buffer circuit.
6 . The solid-state imaging device according to claim 5 , further comprising:
a reference voltage circuit configured to supply a reference voltage to a voltage tap node of the resistor network.
7 . The solid-state imaging device according to claim 1 , wherein the ramp generator circuit includes a plurality of resistor networks, and wherein the ramp generator circuit is configured to switch the voltage tap nodes of one of the resistor networks to the input of one of the buffer circuits.
8 . The solid-state imaging device according to claim 1 ,
wherein each buffer circuit is configured to pass the buffered voltage ramp signal to the second comparator inputs of two or more of the comparator circuits.
9 . The solid-state imaging device according to claim 1 , wherein each buffer circuit is configured to pass the buffered voltage ramp signal to the second comparator input of one of the comparator circuits.
10 . The solid-state imaging device according to claim 1 , wherein each of the at least one resistor networks includes resistor elements electrically connected in series between a first supply node and a second supply node, and wherein the voltage tap nodes are formed between neighboring ones of the resistor elements.
11 . The solid-state imaging device according to claim 1 , further comprising at least two reference voltage circuits, wherein the at least two reference voltage circuits are electrically connected to different voltage tap nodes of at least one of the resistor networks.
12 . The solid-state imaging device according to claim 1 , wherein each buffer circuit includes a low-pass filter circuit configured to smooth the buffered voltage ramp signal.
13 . The solid-state imaging device according to claim 1 , wherein each buffer circuit includes a programmable gain amplifier having a reconfigurable feedback impedance network.
14 . The solid-state imaging device according to claim 1 , further comprising a laminated structure of a first chip and a second chip, wherein the pixel circuits are disposed on the first chip and at least a portion of the ramp generator circuit is disposed on the second chip.
15 . A solid-state imaging device, comprising:
pixel circuits arranged in pixel columns, wherein for each pixel column, signal outputs of the pixel circuits are connected to a data signal line;
comparator circuits, wherein each comparator circuit is configured to generate an active comparator signal in response to a voltage difference between a first comparator input and a second comparator input, and wherein each first comparator input is connected to one of the data signal lines;
a ramp generator circuit including at least one resistor network and buffer circuits; and
at least one reference voltage circuit configured to supply a reference voltage to a voltage tap node of at least one of the resistor networks, wherein
the ramp generator circuit includes a plurality of resistor networks,
the ramp generator circuit is configured to switch the voltage tap nodes of one of the resistor networks to the input of one of the buffer circuits, and
each buffer circuit is configured to pass a buffered voltage ramp signal to the second comparator input of at least one of the comparator circuits.
16 . The solid-state imaging device according to claim 15 , wherein the at least one reference voltage circuit includes a voltage generation circuit adapted to generate a reference voltage and an auxiliary buffer circuit adapted to buffer the generated reference voltage.
17 . The solid-state imaging device according to claim 15 , wherein the at least one reference voltage circuit includes:
a resistor string including resistance elements electrically connected in series between a first auxiliary supply node and a second auxiliary supply node, wherein reference circuit nodes are formed between electrically neighboring resistance elements; and
reference voltage switches, wherein each reference voltage switch is operable to connect one of the reference circuit nodes with an input of the auxiliary buffer circuit.
18 . A solid-state imaging device, comprising:
pixel circuits arranged in pixel columns, wherein for each pixel column, signal outputs of the pixel circuits are connected to a data signal line;
comparator circuits, wherein each comparator circuit is configured to generate an active comparator signal in response to a voltage difference between a first comparator input and a second comparator input, and wherein each first comparator input is connected to one of the data signal lines; and
a ramp generator circuit including at least one resistor network and buffer circuits, wherein the ramp generator circuit is configured to generate a voltage ramp signal based on voltages at voltage tap nodes of the at least one resistor network, wherein
the ramp generator circuit includes a plurality of resistor networks, and wherein the ramp generator circuit is configured to switch the voltage tap nodes of one of the resistor networks to the input of one of the buffer circuit, and
each buffer circuit is configured to pass a buffered voltage ramp signal to the second comparator input of at least one of the comparator circuits.
19 . The solid-state imaging device according to claim 18 , further comprising:
a reference voltage circuit configured to supply a reference voltage to one voltage tap node of each resistor network.
20 . The solid-state imaging device according to claim 18 , further comprising:
reference voltage circuits, wherein each reference voltage circuit is configured to supply a reference voltage to a voltage tap node of one of the resistor networks.