Data transmission chip and electronic device
A data transmission chip and an electronic device are provided, and belong to the field of electronic technologies. A low-speed interface of the data transmission chip is configured to receive a plurality of channels of first signals, and a high-speed serial interface of the data transmission chip is configured to serially transmit the plurality of channels of first signals to another data transmission chip in a form of a data frame.
1 . A data transmission chip, wherein the data transmission chip comprises a high-speed serial interface and a low-speed interface;
the low-speed interface is configured to receive a plurality of channels of first signals; and
the high-speed serial interface is configured to serially transmit the plurality of channels of first signals to another data transmission chip in a form of a data frame, wherein the data frame comprises a frame header, a plurality of data fields, and a gap field located behind each data field, and the plurality of data fields are used to carry data obtained by sampling the plurality of channels of first signals; and
wherein a data transmission rate of the high-speed serial interface is higher than a data transmission rate of the low-speed interface.
2 . The data transmission chip according to claim 1 , wherein
the high-speed serial interface is configured to generate the data frame based on data obtained by sampling the plurality of channels of first signals.
3 . The data transmission chip according to claim 2 , wherein
the high-speed serial interface is configured to sample the plurality of channels of first signals in parallel based on a frequency of a clock signal of the data transmission chip.
4 . The data transmission chip according to claim 3 , wherein the data obtained by sampling comprises a plurality of first sampling sequences sequentially arranged based on a sampling time order, and each first sampling sequence comprises a multi-bit sampling value obtained by sampling the plurality of channels of first signals in parallel for one time.
5 . The data transmission chip according to claim 1 , wherein
the high-speed serial interface is further configured to: receive a plurality of channels of second signals that are serially sent by the another data transmission chip in a form of a data frame, and transmit the plurality of channels of second signals to the low-speed interface.
6 . The data transmission chip according to claim 5 , wherein
the high-speed serial interface is further configured to: sample, based on a frequency of a clock signal of the data transmission chip, the data frame sent by the another data transmission chip, and restore the plurality of channels of second signals based on data obtained by sampling.
7 . The data transmission chip according to claim 6 , wherein the data obtained by sampling the data frame sent by the another data transmission chip comprises a plurality of second sampling sequences sequentially arranged based on a sampling time order, and each second sampling sequence comprises a multi-bit sampling value; and
the high-speed serial interface is further configured to: sequentially obtain a one-bit sampling value from each second sampling sequence, and restore one channel of second signals based on the sequentially obtained multi-bit sampling value.
8 . The data transmission chip according to claim 1 , wherein the data transmission chip and the another data transmission chip are located on a same printed circuit board (PCB); or
the data transmission chip and the another data transmission chip are located on different printed circuit boards.
9 . The data transmission chip according to claim 1 , wherein
the frame header comprises an N-bit first value and an M-bit second value that are consecutive, a length of each data field is W bits, the gap field comprises the M-bit second value, N is a positive integer greater than W, and M is a positive integer less than W.
10 . The data transmission chip according to claim 9 , wherein a difference between N and W is greater than or equal to 2, and M is 1.
11 . The data transmission chip according to claim 9 , wherein the first value is 1, and the second value is 0.
12 . The data transmission chip according to claim 9 , wherein the data frame further comprises a check field located behind the plurality of data fields, and a gap field located behind the check field; and
the check field is used to carry a check bit, and a length of the check field is equal to the length of the data field.
13 . An electronic device, wherein the electronic device comprises a data transmission chip, and wherein the data transmission chip comprises a high-speed serial interface and a low-speed interface;
the low-speed interface is configured to receive a plurality of channels of first signals; and
the high-speed serial interface is configured to serially transmit the plurality of channels of first signals to another data transmission chip in a form of a data frame, wherein the data frame comprises a frame header, a plurality of data fields, and a gap field located behind each data field, and the plurality of data fields are used to carry data obtained by sampling the plurality of channels of first signals; and
wherein a data transmission rate of the high-speed serial interface is higher than a data transmission rate of the low-speed interface.
14 . The electronic device according to claim 13 , wherein
the high-speed serial interface is configured to generate the data frame based on data obtained by sampling the plurality of channels of first signals.
15 . The electronic device according to claim 14 , wherein
the high-speed serial interface is configured to sample the plurality of channels of first signals in parallel based on a frequency of a clock signal of the data transmission chip.
16 . The electronic device according to claim 15 , wherein the data obtained by sampling comprises a plurality of first sampling sequences sequentially arranged based on a sampling time order, and each first sampling sequence comprises a multi-bit sampling value obtained by sampling the plurality of channels of first signals in parallel for one time.
17 . The electronic device according to claim 13 , wherein
the high-speed serial interface is further configured to: receive a plurality of channels of second signals that are serially sent by the another data transmission chip in a form of a data frame, and transmit the plurality of channels of second signals to the low-speed interface.
18 . The electronic device according to claim 17 , wherein the high-speed serial interface is further configured to: sample, based on a frequency of a clock signal of the data transmission chip, the data frame sent by the another data transmission chip, and restore the plurality of channels of second signals based on data obtained by sampling.
19 . The electronic device according to claim 18 , wherein the data obtained by sampling the data frame sent by the another data transmission chip comprises a plurality of second sampling sequences sequentially arranged based on a sampling time order, and each second sampling sequence comprises a multi-bit sampling value; and
the high-speed serial interface is further configured to: sequentially obtain a one-bit sampling value from each second sampling sequence, and restore one channel of second signals based on the sequentially obtained multi-bit sampling value.
20 . A method, comprising:
receiving, by using a low-speed interface of a first data transmission chip, a plurality of channels of first signals; and
serially transmitting, by using a high-speed serial interface of the first data transmission chip, the plurality of channels of first signals to a second data transmission chip in a form of a data frame, wherein the data frame comprises a frame header, a plurality of data fields, and a gap field located behind each data field, and the plurality of data fields are used to carry data obtained by sampling the plurality of channels of first signals, and wherein a data transmission rate of the high-speed serial interface is higher than a data transmission rate of the low-speed interface.