Semiconductor devices and methods of manufacturing thereof

1. A semiconductor device, comprising:

a plurality of first non-planar semiconductor structures disposed in a first area of a substrate, wherein the first non-planar semiconductor structures, parallel with one another, are separated with a first distance; and

a first isolation region collectively embedding a lower portion of each of the first non-planar semiconductor structures and comprising a first layer and a second layer, wherein the second layer is disposed above the first layer, and wherein at least the second layer of the first isolation region is in a cured state.

2. The semiconductor device of claim 1 , further comprising:

a plurality of second non-planar semiconductor structures disposed in a second area of the substrate, wherein the second non-planar semiconductor structures, parallel with one another, are separated with a second distance; and

a second isolation region collectively embedding a lower portion of each of the second non-planar semiconductor structures and comprising a first layer and a second layer, wherein the second layer is disposed above the first layer, and wherein at least the second layer of the second isolation region is in a cured state.

3. The semiconductor device of claim 2 , wherein the first distance is less than the second distance.

4. The semiconductor device of claim 2 , wherein a first height of a non-embedded, upper portion of each of the first non-planar semiconductor structures is equal to a second height of a non-embedded, upper portion of each of the second non-planar semiconductor structures.

5. The semiconductor device of claim 1 , wherein each of the first non-planar semiconductor structures comprises a plurality of first channel layers vertically separated from one another.

6. The semiconductor device of claim 1 , wherein the one of the first and second layers of the first isolation region that is in the cured state is disposed above the other one of first and second layers of the first isolation region that is in an uncured state.

7. The semiconductor device of claim 1 , further comprising:

a first gate structure over a non-embedded, upper portion of each of the first non-planar semiconductor structures.

8. The semiconductor device of claim 1 , wherein the one of the first and second layers of the first isolation region that is in the cured state has a higher density than the other one of first and second layers of the first isolation region that is in an uncured state.

9. The semiconductor device of claim 1 , wherein the first isolation region further comprises a third layer, together with the first and second layers of the first isolation region, that collectively embed the lower portion of each of the first non-planar semiconductor structures.

10. The semiconductor device of claim 9 , wherein the third layer of the first isolation region is in an uncured state and disposed below the first and second layers of the first isolation region.

11. The semiconductor device of claim 9 , wherein the third layer of the first isolation region is in the cured state and disposed above one of the first and second layers of the first isolation region that is in an uncured state.

12. A semiconductor device, comprising:

a plurality of non-planar semiconductor structures, wherein the non-planar semiconductor structures, parallel with one another, are separated with a distance; and

an isolation region collectively embedding a lower portion of each of the non-planar semiconductor structures and comprising at least a first layer and a second layer;

wherein the second layer is disposed above the first layer, and wherein at the second layer of the isolation region is in a cured state and the first layer of the isolation region is in an uncured state.

13. The semiconductor device of claim 12 , wherein each of the non-planar semiconductor structures comprises a plurality of channel layers vertically separated from one another.

14. The semiconductor device of claim 12 , further comprising a gate structure over a non-embedded, upper portion of each of the non-planar semiconductor structures.

15. The semiconductor device of claim 12 , wherein the first layer of the isolation region has a first density and the second layer of the isolation region has a second density, and wherein the second density is higher than the first density.

16. The semiconductor device of claim 12 , wherein the isolation region further comprises a third layer, together with the first and second layers of the isolation region, that collectively embed the lower portion of each of the non-planar semiconductor structures.

17. The semiconductor device of claim 16 , wherein the third layer of the isolation region is in an uncured state and disposed below the first and second layers of the isolation region.

18. The semiconductor device of claim 16 , wherein the third layer of the isolation region is in the cured state and disposed between the first and second layers of the isolation region.

19. A semiconductor device, comprising:

a plurality of non-planar semiconductor structures, wherein the non-planar semiconductor structures, parallel with one another, are separated with a distance; and

an isolation region collectively embedding a lower portion of each of the non-planar semiconductor structures and comprising at least a first layer and a second layer;

wherein the second layer is disposed above the first layer, wherein at the second layer of the isolation region is in a cured state and the first layer of the isolation region is in an uncured state, and wherein the first layer of the isolation region has a first density and the second layer of the isolation region has a second density, and wherein the second density is higher than the first density.

20. The semiconductor device of claim 19 , wherein the isolation region further comprises a third layer, together with the first and second layers of the isolation region, that collectively embed the lower portion of each of the non-planar semiconductor structures.