Error correction decoding device
A decoding device includes a likelihood initialization unit performing initialization process on a storage element for likelihood information used in likelihood calculation of iterative decoding process; a first likelihood calculation unit executing M separate likelihood calculations corresponding to steps 1 to M where M is an integer of 2 or more in likelihood calculation; a second likelihood calculation unit executing M separate likelihood calculations corresponding to steps M+1 to 2M in likelihood calculation of the iterative decoding process; a hard decision unit making hard decision on a likelihood calculation result and generating a decoded bit sequence; a frozen bit removing unit removing a frozen bit and a bit sequence based on a code length of the bit sequence to be decoded from the decoded bit sequence and generating a decoded information bit sequence; and a control unit controlling likelihood calculation of the iterative decoding process.
1 . A decoding device comprising:
processing circuitry configured to:
perform an initialization process on a storage element for likelihood information to be used in likelihood calculation of an iterative decoding process on a basis of likelihood information to be input and a code length of a bit sequence to be decoded;
execute M separate first likelihood calculations corresponding to step 1 to step M where M is an integer of 2 or more, in likelihood calculation of the iterative decoding process;
execute M separate second likelihood calculations corresponding to step M+1 to step 2M in likelihood calculation of the iterative decoding process;
make a hard decision on a result of likelihood calculation and to generate a decoded bit sequence;
remove a frozen bit and a bit sequence based on the code length of the bit sequence to be decoded from the decoded bit sequence and to generate a decoded information bit sequence; and
control likelihood calculation of the iterative decoding process on a basis of the code length of the bit sequence to be decoded, wherein
each of the first likelihood calculations and the second likelihood calculations includes one or more steps,
the processing circuitry is configured to perform the one or more steps of each of the first likelihood calculations and the second likelihood calculations iteratively,
Mt is a positive integer less than or equal to the M, and
the processing circuitry is further configured to perform an initial likelihood calculation process for executing M-Mt separate likelihood calculations corresponding to step 1 to step M−Mt, and an iterative decoding process for iteratively executing Mt separate likelihood calculations corresponding to step M−Mt+1 to step M.
2 . A decoding device comprising:
processing circuitry configured to:
perform an initialization process on a storage element for likelihood information to be used in likelihood calculation of an iterative decoding process on a basis of likelihood information to be input and a code length of a bit sequence to be decoded;
execute M separate first likelihood calculations corresponding to step 1 to step M where M is an integer of 2 or more, in likelihood calculation of the iterative decoding process;
execute M separate second likelihood calculations corresponding to step M+1 to step 2M in likelihood calculation of the iterative decoding process;
make a hard decision on a result of likelihood calculation and to generate a decoded bit sequence;
remove a frozen bit and a bit sequence based on the code length of the bit sequence to be decoded from the decoded bit sequence and to generate a decoded information bit sequence; and
control likelihood calculation of the iterative decoding process on a basis of the code length of the bit sequence to be decoded, wherein
each of the first likelihood calculations and the second likelihood calculations includes one or more steps,
the processing circuitry is configured to perform the one or more steps of each of the first likelihood calculations and the second likelihood calculations iteratively,
Mt is a positive integer less than or equal to the M, and
the processing circuitry is further configured to perform an iterative decoding process for iteratively executing Mt separate likelihood calculations corresponding to step M+1 to step M+Mt, and a terminal likelihood calculation process for executing M−Mt separate likelihood calculations corresponding to step M+Mt+1 to step 2M.