Buck converter and control method thereof
A buck converter includes a switching circuit, an error amplifier, a comparator, a reset circuit, a logic gate, a flip-flop and a driver. The switching circuit generates an output voltage according to an input voltage. The error amplifier generates a compensation voltage signal according to a feedback voltage signal and the reference voltage signal. The feedback voltage signal is associated with the output voltage. The comparator generates a clock set signal according to the compensation voltage signal and a ramp voltage signal. The reset circuit generates a first reset signal according to an on-time control signal. The logic gate generates a second reset signal according to the clock set signal and the first reset signal. The flip-flop generates the on-time control signal according to the clock set signal and the second reset signal. The driver controls the switching circuit according to the on-time control signal.
1 . A buck converter, comprising:
a switching circuit, electrically connected to an input voltage, wherein the switching circuit is configured to generate an output voltage at an output node of the buck converter according to the input voltage;
an error amplifier, configured to receive a feedback voltage signal and generate a compensation voltage signal according to the feedback voltage signal and a first reference voltage signal, wherein the feedback voltage signal is associated with the output voltage;
a first comparator, electrically connected to the error amplifier, wherein the first comparator is configured to generate a clock set signal according to the compensation voltage signal and a ramp voltage signal;
an on-time control circuit, electrically connected to the first comparator, wherein the on-time control circuit comprising:
a reset circuit, configured to generate a first reset signal according to an on-time control signal;
a logic gate, electrically connected to the first comparator and the reset circuit, wherein the logic gate is configured to generate a second reset signal according to the clock set signal and the first reset signal; and
a flip-flop, electrically connected to the logic gate and the first comparator, wherein the flip-flop is configured to generate the on-time control signal according to the clock set signal and the second reset signal; and
a driver, electrically connected to the on-time control circuit and the switching circuit, wherein the driver is configured to control the switching circuit according to the on-time control signal, and
wherein when the clock set signal has a first logic level, the logic gate maintains the second reset signal at a second logic level different from the first logic level, as such the on-time control signal is not reset according to the second reset signal.
2 . The buck converter of claim 1 , wherein the first logic level is a high logic level, and the second logic level is a low logic level.
3 . The buck converter of claim 1 , further comprising:
an inductor, electrically connected between the switching circuit and the output node; and
a feedback circuit, electrically connected to the output node, wherein the feedback circuit is configured to generate the feedback voltage signal according to the output voltage at the output node,
wherein the switching circuit comprises a high-side switch and a low-side switch, and the inductor is electrically connected to the high-side switch and the low-side switch through a phase node.
4 . The buck converter of claim 3 , further comprising:
a sampling unit, electrically connected to the first comparator, wherein the sampling unit is configured to obtain an inductor current flowing through the inductor to generate a voltage drop as the ramp voltage signal according to the inductor current.
5 . The buck converter of claim 3 , further comprising:
a shunt resistor, electrically connected between the inductor and the feedback circuit; and
a detection circuit, electrically connected to two terminals of the shunt resistor, wherein the detection circuit is configured to obtain a voltage difference between the two terminals of the shunt resistor, and is configured to generate the ramp voltage signal according to the obtained voltage difference.
6 . The buck converter of claim 3 , further comprising:
a filter, electrically connected to the phase node, wherein the filter is configured to perform filtering on a current signal associated with the phase node to generate the ramp voltage signal.
7 . The buck converter of claim 3 , wherein the flip-flop comprises a data input pin, a clock input pin, a reset pin and an output pin, and wherein:
the data input pin is configured to receive an enable signal,
the clock input pin is electrically connected to an output terminal of the first comparator, and wherein the clock input pin is configured to receive the clock set signal,
the reset pin is electrically connected to the logic gate, wherein the reset pin is configured to receive the second reset signal, and
the output pin is configured to output the on-time control signal.
8 . The buck converter of claim 7 , wherein the enable signal has the first logic level, and wherein:
when the second reset signal has the second logic level and the clock set signal has the first logic level, the flip-flop generates the on-time control signal having the first logic level, and
when the second reset signal has the first logic level, the flip-flop generates the on-time control signal having the second logic level.
9 . The buck converter of claim 1 , wherein the reset circuit comprises:
a second comparator, comprising a first input terminal configured to receive a second reference voltage signal and a second input terminal electrically connected to a current source;
a capacitor comprising a first terminal electrically connected to the current source and a second terminal electrically connected to a ground terminal; and
a switch, electrically connected to the current source and the ground terminal, and wherein the switch operates according to the on-time control signal.
10 . The buck converter of claim 9 , wherein the reset circuit further comprises an inverter electrically connected to a control terminal of the switch, and an input terminal of the inverter is configured to receive the on-time control signal, and wherein:
when the on-time control signal has the first logic level, the switch is turned off, such that the capacitor is charged by the current source, and the first reset signal output by the second comparator has the first logic level when the capacitor is charged to a voltage level that is greater than the second reference voltage signal, and
when the on-time control signal has the second logic level, the switch is turned on, such that the capacitor is discharged through the ground terminal, and the second comparator outputs the first reset signal having the second logic level when the capacitor is discharged to a voltage level that is less than the second reference voltage signal.
11 . The buck converter of claim 9 , wherein during a period when the compensation voltage signal is greater than the ramp voltage signal, even if a voltage at the first terminal of the capacitor is gradually increased to be greater than the second reference voltage signal, the logic gate maintains the second reset signal at the second logic level.
12 . A control method for a buck converter, the buck converter comprises a switching circuit, an error amplifier, a first comparator, an on-time control circuit and a driver, wherein the first comparator is electrically connected to the error amplifier, the on-time control circuit is electrically connected to the first comparator, the driver is electrically connected to the on-time control circuit and the switching circuit, the on-time control circuit comprises a reset circuit, a logic gate and a flip-flop, the logic gate is electrically connected to the first comparator and the reset circuit, and the flip-flop is electrically connected to the logic gate and the first comparator, and wherein the control method comprises:
generating, by the switching circuit, an output voltage at an output terminal of the buck converter according to an input voltage;
generating, by the error amplifier, a compensation voltage signal according to a feedback voltage signal and a first reference voltage signal, wherein the feedback voltage signal is associated with the output voltage;
generating, by the first comparator, a clock set signal according to the compensation voltage signal and a ramp voltage signal;
generating, by the reset circuit, a first reset signal according to an on-time control signal;
generating, by the logic gate, a second reset signal according to the clock set signal and the first reset signal;
generating, by the flip-flop, the on-time control signal according to the clock set signal and the second reset signal; and
controlling, by the driver, the switching circuit according to the on-time control signal,
when the clock set signal has a first logic level, the second reset signal is maintained, by the logic gate, at a second logic level different from the first logic level, as such the on-time control signal is not reset according to the second reset signal.
13 . The control method of claim 12 , wherein the first logic level is a high logic level, and the second logic level is a low logic level.
14 . The control method of claim 12 , wherein the buck converter further comprises an inductor and a sampling unit, wherein inductor is electrically connected between the switching circuit and an output node of the buck converter, the sampling unit is electrically connected to the first comparator, and wherein the control method further comprises:
obtaining, by the sampling unit, an inductor current flowing through the inductor; and
generating, by the sampling unit, a voltage drop as the ramp voltage signal according to the inductor current.
15 . The control method of claim 12 , wherein the buck converter further comprises an inductor, a shunt resistor and a detection circuit, wherein inductor is electrically connected between the switching circuit and an output node of the buck converter, the shunt resistor is electrically connected between the inductor and the output node of the buck converter, the detection circuit is electrically connected to two terminals of the shunt resistor, and wherein the control method further comprises:
obtaining, by the detection circuit, a voltage difference between the two terminals of the shunt resistor; and
generating, by the detection circuit, the ramp voltage signal according to the obtained voltage difference.
16 . The control method of claim 12 , wherein the buck converter further comprises an inductor and a filter, wherein the switching circuit comprises a high-side switch and a low-side switch, wherein the inductor is electrically connected between the switching circuit and an output node of the buck converter, and the inductor is electrically connected to the high-side switch and the low-side switch through a phase node, wherein the filter is electrically connected to the phase node, wherein the control method further comprises:
performing filtering, by the filter, on a current signal associated with the phase node to generate the ramp voltage signal.
17 . The control method of claim 12 , further comprises:
when the second reset signal has the second logic level and the clock set signal has the first logic level, generating, by the flip-flop, the on-time control signal having the first logic level, and
when the second reset signal has the first logic level, generating, by the flip-flop, the on-time control signal having the second logic level.
18 . The control method of claim 12 , wherein the reset circuit comprises a second comparator, a capacitor and a switch, a first input terminal of the second comparator configured to receive a second reference voltage signal, and the capacitor and the switch connected in parallel between a second input terminal of the second comparator and a ground terminal, and wherein the control method further comprises:
comparing, by the second comparator, a voltage at second input terminal of the second comparator with the second reference voltage signal to generate the first reset signal.
19 . The control method of claim 18 , wherein the reset circuit further comprises an inverter electrically connected to a control terminal of the switch, and an input terminal of the inverter is configured to receive the on-time control signal, and wherein the control method further comprises:
during a period when the switch is turned off due to the on-time control signal having the first logic level, outputting, by the second comparator, the first reset signal having the first logic level when the capacitor is charged to a voltage level that is greater than the second reference voltage signal; and
during a period when the switch is turned on due to the on-time control signal having the second logic level, outputting, by the second comparator, the first reset signal having the second logic level when the capacitor is discharged to a voltage level that is less than the second reference voltage signal.
20 . The control method of claim 18 , wherein during a period when the compensation voltage signal is greater than the ramp voltage signal, maintaining, by the logic gate, the second reset signal at the second logic level, even if a voltage at the second input terminal of the second comparator is gradually increased to be greater than the second reference voltage signal.