Fast-locking phase-locked loop, frequency divider, and communication device
The present disclosure provides a phase-locked loop, a frequency divider and a communication device that enable fast locking. The phase-locked loop comprises a phase frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, a fast-locking control unit and a frequency divider, wherein the frequency divider comprises a plurality of cascaded frequency division units and a reset/set control circuit, the reset/set control circuit being configured to receive the reset signal outputted by the fast-locking control unit, and in response to transition of the reset signal from a low level to the high level, change a state code combination composed of respective state codes of the cascaded frequency division units from the first state to the second state, to cause transition of a feedback signal outputted by the frequency divider from the low level to the high level. With the frequency divider and phase-locked loop, fast locking can be achieved.
1 . A fast-locking phase-locked loop, comprising a phase frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, a fast-locking control unit and a frequency divider,
wherein the fast-locking control unit is configured to output a reset signal at a high level in response to a rising edge of a reference clock signal when receiving a phase-locking enable signal;
the frequency divider comprises a plurality of cascaded frequency division units and a reset/set control circuit, the reset/set control circuit being configured to receive the reset signal outputted by the fast-locking control unit, and in response to transition of the reset signal from a low level to the high level, change a state code combination composed of respective state codes of the cascaded frequency division units from a first state to a second state, to cause transition of a feedback signal outputted by the frequency divider from the low level to the high level; and
the phase frequency detector is configured to output a phase error between the reference clock signal and the feedback signal in response to the reset signal at the high level.
2 . The phase-locked loop according to claim 1 , wherein the frequency divider further comprises a clock output circuit, and each frequency division unit of the cascaded frequency division units comprises a plurality of D-type flip-flops and a combinational logic unit,
wherein an output of one of the D-type flip-flops in said each frequency division unit is configured as a state output of said each frequency division unit, and the clock output circuit is configured to generate the feedback signal of the frequency divider according to respective state outputs of at least two of the cascaded frequency division units.
3 . The phase-locked loop according to claim 1 , wherein each of the cascaded frequency division units comprises a plurality of D-type flip-flops, and the reset/set control circuit includes reset terminals or set terminals respectively provided on the D-type flip-flops.
4 . The phase-locked loop according to claim 3 , wherein the reset/set control circuit is configured to:
in response to the reset signal at the low level, pull low the reset terminals or the set terminals of the plurality of D-type flip-flops in each of the cascaded frequency division units, to cause the state code combination composed of respective state codes of the cascaded frequency division units to be at the first state; and
in response to transition of the reset signal to the high level, pull high the reset terminals or the set terminals of the plurality of D-type flip-flops in each of the cascaded frequency division units, to cause the state code combination composed of respective state codes of the cascaded frequency division units to be changed into the second state.
5 . The phase-locked loop according to claim 1 , wherein the frequency divider comprises a first-stage frequency division unit, a second-stage frequency division unit, and a third-stage frequency division unit, the second-stage frequency division unit and the third-stage frequency division unit being configured to provide respective state outputs to a NAND gate, with an output of the NAND gate being configured as the feedback signal outputted by the frequency divider.
6 . The phase-locked loop according to claim 5 , wherein the first-stage frequency division unit comprises four D-type flip-flops, and the reset/set control circuit comprises: reset terminals respectively provided on a first-stage first D-type flip-flop, a first-stage third D-type flip-flop, and a first-stage fourth D-type flip-flop of the first-stage frequency division unit; a set terminal provided on a first-stage second D-type flip-flop of the first-stage frequency division unit; and a circuit that connects the reset terminals and the set terminal to the output terminal of the fast-locking control unit.
7 . The phase-locked loop according to claim 5 , wherein the second-stage frequency division unit comprises four D-type flip-flops, and the reset/set control circuit comprises: set terminals respectively provided on a second-stage first D-type flip-flop and a second-stage second D-type flip-flop of the second-stage frequency division unit; reset terminals respectively provided on a second-stage third D-type flip-flop and a second-stage fourth D-type flip-flop of the second-stage frequency division unit; and a circuit that connects the reset terminals and the set terminals to the output terminal of the fast-locking control unit.
8 . The phase-locked loop according to claim 5 , wherein the third-stage frequency division unit comprises four D-type flip-flops, and the reset/set control circuit comprises: set terminals respectively provided on a third-stage first D-type flip-flop and a third-stage second D-type flip-flop of the third-stage frequency division unit; reset terminals respectively provided on a third-stage third D-type flip-flop and a third-stage fourth D-type flip-flop of the third-stage frequency division unit; and an AND gate circuit that has input terminals configured to receive the reset signal and a divisor control signal respectively, and an output terminal connected to the reset terminals and the set terminals of the third-stage frequency division unit.
9 . A transceiver comprising a phase-locked loop according to claim 1 .
10 . A frequency divider for a fast-locking phase-locked loop, the frequency divider comprising a plurality of cascaded frequency division units and a reset/set control circuit, the reset/set control circuit being configured to, in response to transition of a reset signal from a low level to a high level, change a state code combination composed of respective state codes of the cascaded frequency division units from a first state to a second state through a reset/set operation, to cause transition of a feedback signal outputted by the frequency divider from the low level to the high level, wherein the reset signal transitions from a low level to a high level in response to a phase-locking enable signal and a rising edge of a reference clock.
11 . The frequency divider according to claim 10 , wherein the frequency divider further comprises a clock output circuit, and each frequency division unit of the cascaded frequency division units comprises a plurality of D-type flip-flops and a combinational logic unit, wherein an output of one of the D-type flip-flops in said each frequency division unit is configured as a state output of said each frequency division unit, and the clock output circuit is configured to generate the feedback signal of the frequency divider according to respective state outputs of at least two of the cascaded frequency division unit.
12 . The frequency divider according to claim 10 , wherein each of the cascaded frequency division units comprises a plurality of D-type flip-flops, and the reset/set control circuit comprises reset terminals or set terminals respectively provided on the D-type flip-flops.
13 . The frequency divider according to claim 10 , wherein the reset/set control circuit is configured to:
in response to the reset signal at the low level, pull low the reset terminals or the set terminals of the plurality of D-type flip-flops in each of the frequency division units, to cause the state code combination composed of respective state codes of the cascaded frequency division units to be at the first state; and
in response to transition of the reset signal to the high level, pull high the reset terminals or the set terminals of the plurality of D-type flip-flops in each of the cascaded frequency division units, to cause the state code combination composed of respective state codes of the cascaded frequency division units to be changed into the second state.
14 . The frequency divider according to claim 10 , wherein the frequency divider comprises a first-stage frequency division unit, a second-stage frequency division unit, and a third-stage frequency division unit, wherein the second-stage frequency division unit and the third-stage frequency division unit are configured to provide respective state outputs to a NAND gate, with an output of the NAND gate being configured as the feedback signal outputted by the frequency divider.
15 . The frequency divider according to claim 14 , wherein the first-stage frequency division unit comprises four D-type flip-flops, and the reset/set control circuit comprises: reset terminals respectively provided on a first-stage first D-type flip-flop, a first-stage third D-type flip-flop, and a first-stage fourth D-type flip-flop of the first-stage frequency division unit; a set terminal provided on a first-stage second D-type flip-flop of the first-stage frequency division unit; and a circuit that connects the reset terminals and the set terminal to the output terminal of the fast-locking control unit.
16 . The frequency divider according to claim 14 , wherein the second-stage frequency division unit comprises four D-type flip-flops, and the reset/set control circuit comprises: set terminals respectively provided on a second-stage first D-type flip-flop and a second-stage second D-type flip-flop of the second-stage frequency division unit; reset terminals respectively provided on a second-stage third D-type flip-flop and a second-stage fourth D-type flip-flop of the second-stage frequency division unit; and a circuit that connects the reset terminals and the set terminals to the output terminal of the fast-locking control unit.
17 . The frequency divider according to claim 14 , wherein the third-stage frequency division unit comprises four D-type flip-flops, and the reset/set control circuit comprises: set terminals respectively provided on a third-stage first D-type flip-flop and a third-stage second D-type flip-flop of the third-stage frequency division unit; reset terminals respectively provided on a third-stage third D-type flip-flop and a third-stage fourth D-type flip-flop of the third-stage frequency division unit; and an AND gate circuit that has input terminals configured to receive the reset signal and a divisor control signal respectively, and an output terminal connected to the reset terminals and the set terminals of the third-stage frequency division unit.