IP Library › Granted Patent US 12,483,236
Granted Patent B2
US 12,483,236 · App. 18/739,482 · Granted Nov 25, 2025

Semiconductor device

Inventors: Sho Tanaka (Tokyo, JP); Tatsuo Harada (Tokyo, JP)
Assignee: Mitsubishi Electric Corporation
H03K17/168H10D12/481H10D62/127H10D62/133
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Quick Facts
Patent No.
US 12,483,236
App. No.
18/739,482
Granted
Nov 25, 2025
Kind
B2
Abstract

An object is to provide a technique that can reduce energy loss during the transient On-period. A semiconductor device includes a first transistor, a second transistor, and a controller. The controller is configured to, before the first transistor enters a transient Off-state, apply a second Off-voltage lower than a first Off-voltage to the second gate, before the first transistor enters a transient On-state, turn On the second transistor, and after the first transistor is turned On, apply the first Off-voltage to the second gate to turn Off the second transistor.

Claims (25)

1 . A semiconductor device comprising:

a first transistor including a first gate and a first emitter region provided along the first gate;

a second transistor adjacent to the first transistor, including a second gate and a second emitter region provided along the second gate; and

a controller configured to control On and Off of the first transistor and the second transistor, wherein,

in plan view, a length of a portion of the second emitter region facing the second gate is greater than a length of a portion of the first emitter region facing the first gate, and

the controller is configured to,

before the first transistor enters a transient Off-state, apply a second Off-voltage lower than a first Off-voltage to the second gate,

before the first transistor enters a transient On-state, turn On the second transistor, and

after the first transistor is turned On, apply the first Off-voltage to the second gate to turn Off the second transistor.

2 . The semiconductor device according to claim 1 , wherein,

in plan view, the first emitter region is provided intermittently along the first gate, and the second emitter region is provided continuously along the second gate.

3 . The semiconductor device according to claim 1 , wherein,

in plan view, the first emitter region is provided intermittently along the first gate, and the second emitter region is provided intermittently along the second gate.

4 . The semiconductor device according to claim 1 , wherein,

in plan view, the first emitter region and the second emitter region are connected to each other.

5 . The semiconductor device according to claim 1 , wherein

a peak of an impurity concentration of the second emitter region is larger than a peak of an impurity concentration of the first emitter region.

6 . The semiconductor device according to claim 1 , wherein

0<Δt1<tm is satisfied wherein Δt1 represents time from when the second transistor is turned On until the first transistor is turned On, and tm represents Miller interval of the second transistor.

7 . The semiconductor device according to claim 1 , wherein,

while the first transistor is in the transient On-state, a voltage of the first gate exceeds a Miller voltage before a voltage of the second gate falls below the Miller voltage.

8 . The semiconductor device according to claim 1 , wherein,

when the first transistor enters the transient Off-state immediately after the transient On-state, the controller is configured to change the voltage of the second gate from the On-voltage to the second Off-voltage without maintaining the voltage of the second gate at the first Off-voltage.

9 . The semiconductor device according to claim 1 , wherein

the second Off-voltage is 0V or higher.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 11, 2024
From: TANAKA, SHO; HARADA, TATSUO
To: MITSUBISHI ELECTRIC CORPORATION
Reel/Frame 067684/0946 →
Priority Claims (1)
JP 2023-162433 · Sep 26, 2023 · national
Continuity (1)
Related Publication 20250105837A1 · Mar 27, 2025
References Cited (4)
US 20050161768A1 · Sugiyama · 2005 [cited by examiner]
US 20250105837A1 · Tanaka · 2025 [cited by examiner]
JP 2004319624A · 2004 [cited by applicant]
JP 2005191221A · 2005 [cited by applicant]