IP Library Granted Patent US 12,487,493
Granted Patent B2
US 12,487,493 · App. 18/742,207 · Granted Dec 2, 2025

Display device

Inventor: Hitoshi Tanaka (Tokyo, JP)
Assignee: Magnolia White Corporation
G02F1/134309G02F1/136227G02F1/1368H10D30/6729H10D86/423H10D86/451H10D86/60
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Quick Facts
Patent No.
US 12,487,493
App. No.
18/742,207
Granted
Dec 2, 2025
Kind
B2
Abstract

According to one embodiment, a display device includes a first inorganic insulating film covering an oxide semiconductor layer and a protective metal layer, a second inorganic insulating film covering a gate electrode, a first connection electrode in contact with the protective metal layer at a first opening portion which penetrates through the first inorganic insulating film and the second inorganic insulating film, a first organic insulating film covering the first connection electrode, and a second connection electrode in contact with the first connection electrode at a second opening portion which penetrates through the first organic insulating film, wherein the second opening portion is located above the first opening portion.

Claims (38)

1 . A semiconductor device comprising:

an insulating substrate;

an oxide semiconductor layer arranged on the insulating substrate;

a first inorganic insulating film covering the oxide semiconductor layer;

a gate electrode provided on the first inorganic insulating film, wherein

a second inorganic insulating film is provided on the first inorganic insulating film, and covers the gate electrode,

a first opening penetrates through the first inorganic insulating film and the second inorganic insulating film,

a first organic insulating film is provided on the second inorganic insulating film,

a second opening penetrates through the first organic insulating film and overlaps the first opening in plan view,

a second organic insulating film is provided on the first organic insulating film,

a third opening penetrates through the second organic insulating film,

a third inorganic insulating film is provided on the second organic insulating film,

a fourth opening penetrates through the third inorganic insulating film, and overlaps the third opening in plan view,

a first electrode arranged between the second inorganic insulating film and the first organic insulating film,

a second electrode arranged between the first organic insulating film and the second organic insulating film,

a third electrode arranged between the second organic insulating film and the third inorganic insulating film, and

a fourth electrode arranged on the third inorganic insulating film, wherein

the first electrode is connected to the second electrode in a first area overlapping the first opening and the second opening,

the third electrode is connected to the second electrode in a second area overlapping the third opening and the fourth opening, and

the second area is disposed offset from the first area in plan view.

2 . The semiconductor device of claim 1 , wherein

an entire periphery of a first edge that defines the first opening is located on an inner side of a second edge that defines the second opening in plan view.

3 . The semiconductor device of claim 1 , wherein

the second organic insulating film is thinner than the first organic insulating film.

4 . The semiconductor device of claim 1 , wherein

the third opening is located between the gate electrode and the second opening in plan view.

5 . The semiconductor device of claim 1 , wherein

an entire periphery of a third edge that defines the third opening is located on an inner side of a fourth edge that defines the fourth opening in plan view.

6 . The semiconductor device of claim 1 , wherein

the fourth opening overlaps the second opening in plan view.

7 . The semiconductor device of claim 1 , wherein

the first electrode is electrically connected to the oxide semiconductor layer in the first opening.

8 . The semiconductor device of claim 1 , wherein

the third electrode is connected to the fourth electrode in the fourth opening.

9 . The semiconductor device of claim 1 , wherein

each of the first electrode and the second electrode is a stacked layer body in which a plurality of metal layers are stacked.

10 . The semiconductor device of claim 1 , wherein

each of the third electrode and the fourth electrode is a transparent electrode.

Assignments (2)
CHANGE OF NAME Recorded Aug 27, 2025
From: JAPAN DISPLAY INC.
To: MAGNOLIA WHITE CORPORATION
Reel/Frame 073057/0042 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 13, 2024
From: TANAKA, HITOSHI
To: JAPAN DISPLAY INC.
Reel/Frame 067718/0388 →
Priority Claims (1)
JP 2019-001266 · Jan 8, 2019 · national
Continuity (3)
Continuation 17305403 · Jul 7, 2021
Continuation PCTJP2019048124 · Dec 9, 2019
Related Publication 20240329465A1 · Oct 3, 2024
References Cited (7)
US 20160204180A1 · Lee et al. · 2016 [cited by applicant]
US 20170025444A1 · Hirakata · 2017 [cited by applicant]
US 20180083084A1 · Kim et al. · 2018 [cited by applicant]
US 20200105843A1 · Baek · 2020 [cited by examiner]
US 20210043873A1 · Sung · 2021 [cited by examiner]
JP 2010039810A · 2010 [cited by applicant]
Office Action issued on Aug. 22, 2023, in corresponding Japanese Application No. 2022-170776, 8 pages. [cited by applicant]