System and method for in-memory image processing
View Patent ↗A system and method for in-memory image processing. In some embodiments, a system includes a memory, a first neuron processing circuit, and a second neuron processing circuit. The first neuron processing circuit may be connected to a first plurality of bit lines of the memory, and the second neuron processing circuit may be connected to a second plurality of bit lines of the memory. The first neuron processing circuit may include a plurality of configurable processing circuits, each of the configurable processing circuits including: an artificial neuron for calculating the sign of a weighted sum of a plurality of single-bit digital input signals at respective inputs of the artificial neuron, and a plurality of multiplexers, each having an output connected to a respective input of the inputs of the artificial neuron.
1 . A system comprising:
a memory comprising a Dynamic Random Access Memory (DRAM);
a first neuron processing circuit; and
a second neuron processing circuit,
the first neuron processing circuit being connected to a first plurality of bit lines of the memory,
the second neuron processing circuit being connected to a second plurality of bit lines of the memory,
the first neuron processing circuit comprising a plurality of configurable processing circuits,
each of the configurable processing circuits comprising:
an artificial neuron for calculating the sign of a weighted sum of a plurality of single-bit digital input signals at respective inputs of the artificial neuron, and
a plurality of multiplexers, each having an output connected to a respective input of the inputs of the artificial neuron,
wherein:
the artificial neuron comprises:
a left input network (LIN) to calculate a first contribution to the weighted sum, the first contribution comprising a sum of terms with positive weights;
a right input network (RIN) to calculate a second contribution to the weighted sum, the second contribution comprising a sum of terms with negative weights;
a sense amplifier connected to the LIN and to the RIN; and
a set-reset latch connected to the sense amplifier,
the LIN comprises a first set of switchable current sources,
each switchable current source of the first set of switchable current sources is configured:
to be switched on or off according to whether the value at a respective corresponding input of the LIN is a one or a zero; and
to drive an output of the LIN,
the RIN comprises a second set of switchable current sources,
each switchable current source of the second set of switchable current sources is configured:
to be switched on or off according to whether the value at a respective corresponding input of the RIN is a one or a zero; and
to drive an output of the RIN, and
the DRAM and the first and second neuron processing circuits are in a same semiconductor chip.
2 . The system of claim 1 , wherein each of the configurable processing circuits of the first neuron processing circuit is connected to each of the other configurable processing circuits of the first neuron processing circuit.
3 . The system of claim 1 , wherein each of the configurable processing circuits of the first neuron processing circuit further comprises a register for storing one or more bits.
4 . The system of claim 1 , wherein the weighted sum is a weighted sum of four terms.
5 . The system of claim 4 , wherein the weights corresponding to the four terms are 1, 1, 1, and −2.
6 . The system of claim 1 , wherein the memory, the first neuron processing circuit, and the second neuron processing circuit are fabricated on a single semiconductor chip.
7 . A system comprising:
a memory comprising a Dynamic Random Access Memory (DRAM);
a first neuron processing circuit; and
a second neuron processing circuit,
the first neuron processing circuit being connected to a first plurality of bit lines of the memory,
the second neuron processing circuit being connected to a second plurality of bit lines of the memory,
the first neuron processing circuit comprising:
a plurality of multiplexers and being configured to perform:
a multi-bit addition when the multiplexers receive a first set of control signals, and
a multi-bit comparison when the multiplexers receive a second set of control signals,
a plurality of configurable processing circuits, a first configurable processing circuit of the configurable processing circuits comprising:
an artificial neuron for calculating the sign of a weighted sum of a plurality of single-bit digital input signals at respective inputs of the artificial neuron, the artificial neuron comprising:
a left input network (LIN) to calculate a first contribution to the weighted sum, the first contribution comprising a sum of terms with positive weights;
a right input network (RIN) to calculate a second contribution to the weighted sum, the second contribution comprising a sum of terms with negative weights;
a sense amplifier connected to the LIN and to the RIN; and
a set-reset latch connected to the sense amplifier,
wherein the LIN comprises a first set of switchable current sources,
wherein each switchable current source of the first set of switchable current sources is configured:
to be switched on or off according to whether the value at a respective corresponding input of the LIN is a one or a zero; and
to drive an output of the LIN,
wherein the RIN comprises a second set of switchable current sources,
wherein each switchable current source of the second set of switchable current sources is configured:
to be switched on or off according to whether the value at a respective corresponding input of the RIN is a one or a zero; and
to drive an output of the RIN, and
wherein the DRAM and the first and second neuron processing circuits are in a same semiconductor chip.
8 . The system of claim 7 , wherein the first configurable processing circuit of the configurable processing circuits further comprising:
a plurality of the multiplexers of the first neuron processing circuit, each of the plurality of multiplexers of the first configurable processing circuit having an output connected to a respective input of the inputs of the artificial neuron.
9 . The system of claim 8 , wherein each of the configurable processing circuits of the first neuron processing circuit is connected to each of the other configurable processing circuits of the first neuron processing circuit.
10 . The system of claim 8 , wherein each of the configurable processing circuits of the first neuron processing circuit further comprises a register for storing one or more bits.
11 . The system of claim 8 , wherein the weighted sum is a weighted sum of four terms.
12 . The system of claim 11 , wherein the weights corresponding to the four terms are 1, 1, 1, and −2.
13 . The system of claim 7 , wherein the memory, the first neuron processing circuit, and the second neuron processing circuit are fabricated on a single semiconductor chip.
14 . A method for computing, by a system,
the system comprising:
a memory comprising a Dynamic Random Access Memory (DRAM);
a first neuron processing circuit; and
a second neuron processing circuit,
the first neuron processing circuit being connected to a first plurality of bit lines of the memory,
the second neuron processing circuit being connected to a second plurality of bit lines of the memory,
the first neuron processing circuit comprising a plurality of configurable processing circuits,
a first configurable processing circuit of the configurable processing circuits comprising:
an artificial neuron for calculating the sign of a weighted sum of a plurality of single-bit digital input signals at respective inputs of the artificial neuron, and
a plurality of multiplexers, each having an output connected to a respective input of the inputs of the artificial neuron,
wherein:
the artificial neuron comprises:
a left input network (LIN) to calculate a first contribution to the weighted sum, the first contribution comprising a sum of terms with positive weights;
a right input network (RIN) to calculate a second contribution to the weighted sum, the second contribution comprising a sum of terms with negative weights;
a sense amplifier connected to the LIN and to the RIN; and
a set-reset latch connected to the sense amplifier,
the LIN comprises a first set of switchable current sources,
each switchable current source of the first set of switchable current sources is configured:
to be switched on or off according to whether the value at a respective corresponding input of the LIN is a one or a zero; and
to drive an output of the LIN,
the RIN comprises a second set of switchable current sources,
each switchable current source of the second set of switchable current sources is configured:
to be switched on or off according to whether the value at a respective corresponding input of the RIN is a one or a zero; and
to drive an output of the RIN, and
the method comprising:
applying a first sequence of control signals to the multiplexers of the first configurable processing circuit; and
in response to the first sequence of control signals, calculating a sum, by the first configurable processing circuit,
wherein the DRAM and the first and second neuron processing circuits are in a same semiconductor chip.
15 . The method of claim 14 , further comprising:
applying a second sequence of control signals to the multiplexers of the first configurable processing circuit; and
in response to the first sequence of control signals, performing a comparison, by the first configurable processing circuit.
16 . The method of claim 14 , wherein the sum is a sum of:
a first binary integer, left-shifted by a first number of bit positions, and
a second binary integer, left-shifted by a second number of bit positions,
the second number of bit positions being different from the first number of bit positions.
17 . The method of claim 16 , further comprising forming the second binary integer as a subset of bits of a third binary integer.
18 . The method of claim 14 , further comprising calculating an approximate product of a first integer and a second integer,
the calculating comprising:
subtracting a third integer from the first integer to form a difference, and
left-shifting the difference by a first number of bit positions,
wherein:
the third integer is determined based on the first integer;
the first number of bit positions is based on the second integer; and
the left-shifting of the difference corresponds to multiplying the difference by a fourth integer, the fourth integer being the closest power of 2 to the second integer.
19 . The method of claim 18 , wherein the third integer is determined by:
determining that the first integer is within a first range of values, the first range of values being based on a previously performed comparison, and
setting the third integer equal to a value associated with the first range of values.
20 . The method of claim 14 , wherein the memory, the first neuron processing circuit, and the second neuron processing circuit are fabricated on a single semiconductor chip.