Virtual partitioning a processor-in-memory (“PIM”)
Process isolation for a PIM device includes: receiving, from a process, a call to allocate a virtual address space where the process stores a PIM configuration context; allocating the virtual address space including mapping a physical address space including PIM device configuration registers to the virtual address space only if the physical address space is not mapped to another process's virtual address space; and programming the PIM device configuration space according to the configuration context. When a PIM command is executed, a translation mechanism determines whether there is a valid mapping of a virtual address of the PIM command to a physical address of a PIM resource, such as a LIS entry. If a valid mapping exists, the translation is completed and the resource is accessed, but if there is not a valid mapping, the translation fails and the process is blocked from accessing the PIM resource.
1 . An apparatus comprising:
a processor; and
a processing-in-memory (PIM) controller coupled to the processor, wherein the PIM controller is configured to:
receive, from a process, a PIM instruction that targets a virtual address of a virtualized PIM configuration, wherein the virtualized PIM configuration includes a configuration context associated with a PIM device; and
translate, based on a valid mapping of a virtual address space of the process to a physical address space of a PIM resource, the virtual address to a physical address of the PIM resource.
2 . The apparatus of claim 1 , wherein a virtual address space of the virtualized PIM configuration is mapped to the physical address space of the PIM resource.
3 . The apparatus of claim 2 , wherein the virtual address space of the virtualized PIM configuration is mapped to the physical address space of the PIM resource in response to no other process being mapped to the physical address space of the PIM resource.
4 . The apparatus of claim 2 , wherein a virtual instruction store of the virtualized PIM configuration is mapped to a local instruction store on a PIM device; and
wherein to translate the virtual address to the physical address of the PIM resource the PIM controller is configured to:
translate the virtual address to a physical address in the local instruction store on the PIM device.
5 . The apparatus of claim 2 , wherein a page of the virtual address space of the process is mapped to a physical address space of a memory buffer on a PIM device; and
wherein to translate the virtual address to the physical address of the PIM resource the PIM controller is configured to:
translate the virtual address to a physical address of the memory buffer on the PIM device.
6 . The apparatus of claim 2 , wherein the virtual address space of the process is mapped to a physical address space of one or more registers on a PIM device; and
wherein to translate the virtual address to the physical address of the PIM resource the PIM controller is configured to:
translate the virtual address to a physical address of a register on the PIM device.
7 . The apparatus of claim 1 further comprising:
a PIM driver configured to program the PIM resource with data of the virtualized PIM configuration including programming at least one of a local instruction store and one or more PIM registers.
8 . The apparatus of claim 1 further comprising:
a memory controller configured to issue, based on the PIM instruction, a PIM command targeting the physical address of the PIM resource.
9 . The apparatus of claim 1 further comprising a PIM-enabled memory device that includes the PIM resource.
10 . A method comprising:
receiving, from a process, a PIM instruction that targets a virtual address of a virtualized PIM configuration, wherein the virtualized PIM configuration includes a configuration context associated with a PIM device; and
translating, based on a valid mapping of a virtual address space of the process to a physical address space of a PIM resource, the virtual address to a physical address of the PIM resource.
11 . The method of claim 10 further comprising:
mapping a virtual address space of the virtualized PIM configuration to the physical address space of the PIM resource.
12 . The method of claim 11 , wherein the virtual address space of the virtualized PIM configuration is mapped to the physical address space of the PIM resource in response to no other process being mapped to the physical address space of the PIM resource.
13 . The method of claim 11 , wherein mapping the virtual address space of the virtualized PIM configuration to the physical address space of the PIM resource includes:
mapping a virtual instruction store of the virtualized PIM configuration to a local instruction store on a PIM device; and
wherein translating the virtual address to the physical address of the PIM resource includes:
translating the virtual address to a physical address in the local instruction store on the PIM device.
14 . The method of claim 11 , wherein mapping the virtual address space of the virtualized PIM configuration to the physical address space of the PIM resource includes:
mapping a page of the virtual address space of the process to a physical address space of a memory buffer on a PIM device; and
wherein translating the virtual address to the physical address of the PIM resource includes:
translating the virtual address to a physical address of the memory buffer on the PIM device.
15 . The method of claim 11 , wherein mapping the virtual address space of the virtualized PIM configuration to the physical address space of the PIM resource includes:
mapping the virtual address space of the process to a physical address space of one or more registers on a PIM device; and
wherein translating the virtual address to the physical address of the PIM resource includes:
translating the virtual address to a physical address of a register on the PIM device.
16 . The method of claim 10 further comprising:
programming the PIM resource with data of the virtualized PIM configuration including programming at least one of a local instruction store and one or more PIM registers.
17 . The method of claim 10 further comprising:
issuing, based on the PIM instruction, a PIM command targeting the physical address of the PIM resource.
18 . An apparatus comprising:
a processor;
a computer memory coupled to the processor, the computer memory storing computer executable instructions that, when executed by the processor, cause the apparatus to:
store, by a process, a processing-in-memory (PIM) configuration context included in a virtualized PIM configuration using a virtual address space assigned to the process, the PIM configuration context associated with a PIM device and including a virtual instruction store; and
generate, by the process, a PIM instruction targeting a virtual memory address in the virtual address space, the virtual memory address corresponding to an entry in the virtual instruction store.
19 . The apparatus of claim 18 , wherein a portion of the virtual address space that corresponds to the virtual instruction store is mapped to a physical address space of a local instruction store on a PIM device.