Approach Uniform NAND Cell State Transition over Program Erase Cycles Using Look Up Table

1 . A method for randomizing memory storage data, comprising:

receiving at a data inverter user data and meta data sequence having an inversion seed bit;

determining a value for the inversion seed bit from a look up table specifying inversion seeds for different pages of data to be stored in a memory;

depending on the value of the inversion seed bit, bit-flipping the user data and meta data sequence except for the inversion seed bit; and

regardless of bit-flipping, exclusive ORing (XORing) the user data and meta data sequence with a random sequence to produce an XORed sequence for storage in the memory as randomized data.

2 . The method of claim 1 , further comprising:

appending an error correction code to the data sequence prior to the XORing of the data sequence with the random sequence; and

storing the XORed sequence in the memory as the randomized data.

3 . The method of claim 1 , further comprising:

appending an error correction code to the data sequence after the XORing of the data sequence with the random sequence; and

storing the XORed sequence in the memory as the randomized data.

4 . The method of claim 1 , wherein the look up table comprises randomly generated entries generated with a seed comprising a) a physical address where the data sequence is to be stored in the memory and b) a program erase count for the physical address.

5 . The method of claim 4 , wherein the look up table comprising the randomly generated entries comprises inversion seeds for each type of page data to be written to the physical address in the memory.

6 . The method of claim 5 , wherein

the memory comprises a triple-level cell (TLC) NAND device, and

the inversion seeds comprise inversion seeds for most significant bit, center significant bit, and least significant bit pages.

7 . The method of claim 5 , wherein

the memory comprises a quadruple-level cell (QLC) NAND device, and

the inversion seeds comprise inversion seeds for most significant bit, center most significant bit, center least significant bit, and least significant bit pages.

8 . The method of claim 1 , wherein

the bit-flipping of the data sequence comprises bit-flipping bits for a page of data to be stored, and

the bit-flipping transitions the data to be stored from an initial program state to a final program state of the memory.

9 . The method of claim 8 , wherein a number of transitions from the initial program state to the final program state approaches uniformity between all program states in the memory.

10 . The method of claim 9 , wherein the number of transitions from the initial program state to the final program state is distributed between all program states in the memory with a deviation ranging from 0.01% to 2%.

11 . A memory system, comprising:

a memory;

a randomizer coupled to the memory; and

a data inverter coupled to the randomizer, wherein the data inverter is configured to:

receive a data sequence including user data and meta data having an inversion seed bit;

determine a value for the inversion seed bit from a look up table specifying inversion seeds for different pages of data to be stored in the memory; and

depending on the value of the inversion seed, bit-flip the data sequence except for the inversion seed bit, and

wherein the randomizer is configured, regardless of bit-flipping, exclusive OR (XOR) the data sequence with a random sequence R for storage in the memory as randomized data.

12 . The memory system of claim 11 , further comprising an encoder configured to:

append an error correction code to the data sequence prior to XORing of the data sequence with the random sequence; and

send the XORed sequence to the memory for storage as the randomized data.

13 . The memory system of claim 11 , further comprising an encoder configured to:

append an error correction code to the data sequence after XORing of the data sequence with the random sequence; and

send the XORed sequence to the memory for storage as the randomized data.

14 . The memory system of claim 11 , wherein the look up table comprises randomly generated entries generated with a seed comprising a) a physical address where the data sequence is to be stored in the memory and b) a program erase count for the physical address.

15 . The memory system of claim 14 , wherein the look up table comprising the randomly generated entries comprises inversion seeds for each type of page data to be written to the physical address in the memory.

16 . The memory system of claim 15 , wherein

the memory comprises a triple-level cell (TLC) NAND device, and

the inversion seeds comprise inversion seeds for most significant bit, center significant bit, and least significant bit pages.

17 . The memory system of claim 15 , wherein

the memory comprises a quadruple-level cell (QLC) NAND device, and

the inversion seeds comprise inversion seeds for most significant bit, center most significant bit, center least significant bit, and least significant bit pages.

18 . The memory system of claim 11 , wherein the data inverter is configured to bit-flip bits for a page of data to be stored, and

the bit-flipping transitions the data to be stored from an initial program state to a final program state of the memory.

19 . The memory system of claim 19 , wherein a number of transitions from the initial program state to the final program state approaches uniformity between all program states in the memory.

20 . The memory system of claim 19 , wherein the number of transitions from the initial program state to the final program state is distributed between all program states in the memory with a deviation ranging from 0.01% to 2%.