Chip heat treatment system
A system includes a rack, a heat treatment device configured to perform a heat treatment, one or more conveyance devices, and a host. The host is configured to determine a target memory chip to be subjected to the heat treatment by the heat treatment device among memory chips in a plurality of drives mounted on the rack, and disable communication with a target drive on which the target memory chip is mounted. The host is configured to control the conveyance devices to dismount the target drive from the rack, detach a component including the target memory chip from the target drive, convey the detached component to the heat treatment device, reattach the component including the target memory chip that has undergone the heat treatment to a drive, and mount the drive with the component including the target memory chip that has undergone the heat treatment on the rack.
1 . A chip heat treatment system comprising:
a rack on which a plurality of drives is mountable;
a heat treatment device configured to perform a heat treatment;
one or more conveyance devices; and
a host configured to perform writing and reading of data with respect to one or more memory chips in each of the drives mounted on the rack, wherein the host is configured to:
determine a target memory chip to be subjected to the heat treatment among memory chips in the plurality of drives mounted on the rack;
disable communication with a target drive on which the target memory chip is mounted;
control the one or more conveyance devices to:
dismount the target drive from the rack;
detach a component including the target memory chip from the target drive;
convey the detached component to the heat treatment device;
reattach the component including the target memory chip that has undergone the heat treatment to a drive; and
mount the drive with the component including the target memory chip that has undergone the heat treatment on the rack; and
enable communication with the mounted drive.
2 . The chip heat treatment system according to claim 1 , wherein the one or more conveyance devices includes:
a drive conveyance device configured to dismount a drive from the rack and mount a drive to the rack;
a first conveyance device configured to detach a component including a memory chip from a drive and attach a component including a memory chip to a drive; and
a second conveyance device configured to convey the component detached by the first conveyance device to the heat treatment device.
3 . The chip heat treatment system according to claim 2 , wherein the one or more conveyance devices further includes a rack conveyance device configured to convey the rack.
4 . The chip heat treatment system according to claim 2 , wherein the drive conveyance device is configured to collectively detach a plurality of drives from the rack and collectively attach a plurality of drives to the rack.
5 . The chip heat treatment system according to claim 2 , wherein
each of the heat treatment device, the drive conveyance device, the first conveyance device, and the second conveyance device is movable, and
the host is configured to control each of the heat treatment device, the drive conveyance device, the first conveyance device, and the second conveyance device to move to the rack.
6 . The chip heat treatment system according to claim 2 , wherein each of the drive conveyance device, the first conveyance device, and the second conveyance device includes a robot arm for conveying items picked up by the robot arm.
7 . The chip heat treatment system according to claim 1 , wherein the heat treatment device includes a connector connectable to the component and is configured to perform an operation test with respect to a memory chip of the component connected to the connector.
8 . The chip heat treatment system according to claim 7 , wherein the host is configured to issue an instruction to discard the target memory chip when the result of the operation test indicates that the target memory chip is not functioning normally.
9 . The chip heat treatment system according to claim 7 , wherein the host is configured to disable communication with the target memory chip when the result of the operation test indicates that the target memory chip is not functioning normally and the drive with the component including the target memory that has undergone the heat treatment is mounted on the rack.
10 . The chip heat treatment system according to claim 1 , wherein the host is configured to copy data stored in the target memory chip to a memory chip in a non-target drive mounted on the rack before disabling the communication with the target memory chip.
11 . The chip heat treatment system according to claim 10 , wherein the host is configured to erase the data stored in the target memory chip and write data of a predetermined value into each memory cell of the target memory chip before disabling the communication with the target memory chip.
12 . The chip heat treatment system according to claim 11 , wherein a threshold voltage corresponding to the predetermined value is higher than a lowest threshold voltage among threshold voltages corresponding to a plurality of data values that can be stored in the memory cell, and lower than a highest threshold voltage among the threshold voltages corresponding to the plurality of data values that can be stored in the memory cell.
13 . The chip heat treatment system according to claim 11 , wherein the host is configured to issue a data erasure certificate with respect to the target memory chip after the data stored in the target memory chip is erased.
14 . The chip heat treatment system according to claim 1 , wherein the host is configured to determine a performance level of the target memory chip, and determine a temperature and a duration of the heat treatment by the heat treatment device based on the performance level.
15 . The chip heat treatment system according to claim 1 , wherein the host is configured to determine a performance level of a memory chip in a drive mounted on the rack, and determine a memory chip of which performance level drops below a threshold level to be the target memory chip.
16 . The chip heat treatment system according to claim 15 , wherein the host is configured to determine the performance level of the memory chip based on at least one of a read latency, a write latency, a read throughput, and a write throughput.
17 . The chip heat treatment system according to claim 15 , wherein the host is configured to determine the target memory chip based on at least one of an amount of time that has elapsed since a last heat treatment to the memory chip and a number of times the heat treatment has been performed with respect to the memory chip.
18 . The chip heat treatment system according to claim 1 , wherein the host is configured to control the one or more conveyance devices to affix, to the component including the target memory chip, a label having an indicator that changes state in an irreversible manner when the label is subjected to a temperature that is above a predetermined temperature, and convey the component with the label to the heat treatment device.
19 . The chip heat treatment system according to claim 18 , wherein the host is configured to determine whether or not the heat treatment has been properly performed with respect to the target memory chip based on a state of the indicator.
20 . The chip heat treatment system according to claim 1 , wherein the host is configured to control the one or more conveyance devices to affix, to the component including the target memory chip that has undergone the heat treatment, a label having an indicator that changes state in an irreversible manner in when subjected to a temperature that is above a predetermined temperature.