Electrical interconnects for packages containing photonic integrated circuits
A system-in-package includes: a photonic integrated circuit (PIC) including an active photonic component; and an electronic integrated circuit (EIC) stacked on the PIC, the EIC including: an electrical component electrically connected to a landing pad, and a copper pillar embedded in the landing pad and protruding from the landing pad that connects with the active photonic component such that the electrical component is electrically connected to the active photonic component. The landing pad has a larger surface area than a cross sectional area of the copper pillar, and wherein, when viewed from the EIC towards the PIC, the active photonic component on the PIC is offset from the landing pad of the EIC, wherein the offset is sufficient to keep a parasitic capacitance between the landing pad and the active photonic component within a pre-determined threshold level of tolerance.
1. A system-in-package comprising:
a photonic integrated circuit (PIC) comprising a substrate supporting an electro-absorption modulator (EAM) and one or more patterned electrically conducting layers between the EAM and a first surface of the PIC, the EAM comprising a diode junction and a pair of electrodes on opposing sides of the diode junction, a first electrode of the pair of electrodes being electrically connected to an electrical contact at the first surface of the PIC by the one or more patterned electrically conducting layers, and a second electrode of the pair of electrodes being electrically connected to an electrical contact at a second surface of the PIC by one or more vias extending through the substrate, the first surface of the PIC being opposite the second surface of the PIC; and
an electronic integrated circuit (EIC) stacked on the first surface of the PIC, the EIC comprising a driver electrically connected to an electrical contact at a first surface of the EIC facing the first surface of the PIC,
wherein the electrical contact on the first surface of the EIC is electrically connected to the electrical contact on the first surface of the PIC.
2. The system of claim 1 , wherein the EIC is configured so that during operation the driver drives the modulator by applying an alternating current (AC) electrical signal to the first electrode during operation to encode an optical signal in a waveguide in the PIC with data.
3. The system of claim 2 , wherein the first electrode is a cathode.
4. The system of claim 3 , wherein the EIC is configured so that the time-varying electrical signal comprises a positive voltage.
5. The system of claim 2 , wherein the system is configured to apply a direct current (DC) voltage signal to the second electrode during operation.
6. The system of claim 1 , wherein the second electrode is grounded.
7. The system of claim 1 , wherein the first electrode is a cathode, and the second electrode is an anode.
8. The system of claim 1 , wherein the electrical contact on the first surface of the EIC is electrically connected to one of the electrical contacts on the top surface of the PIC by a copper pillar.
9. The system of claim 1 , wherein the PIC comprises multiple EAMs, each electrically connected to a corresponding driver in the EIC via a respective copper post.
10. The system of claim 1 , wherein the diode junction comprises germanium silicon.
11. The system of claim 1 , wherein the electrical contact on the top surface of the PIC is laterally offset from the first electrode of the EAM.
12. The system of claim 1 , wherein the driver is a component of an AMS block that is electrically connected to a compute block.
13. The system of claim 12 , wherein the EIC includes the compute block.
14. The system of claim 1 , wherein the driver is a component in an AMS block that is electrically connected to a memory device.
15. The system of claim 14 , wherein the memory device is a high bandwidth memory (HBM) device.
16. The system-in-package of claim 15 , wherein the HBM device is electrically connected to the AMS block via electrical connections in the PIC.
17. A method of forming a system-in-package, comprising:
providing a photonic integrated circuit (PIC) comprising an active photonic component and one or more patterned electrically conducting layers between the active photonic component and a first side of the PIC, the active photonic component comprising a diode junction and a pair of electrodes on opposing sides of the diode junction, a first electrode of the pair of electrodes being electrically connected to an electrical contact at the first side of the PIC by the one or more patterned electrically conducting layers, and a second electrode of the pair of electrodes being electrically connected to an electrical contact at a second side of the PIC by one or more vias extending through the substrate;
providing an electronic integrated circuit (EIC) comprising a driver electrically connected to an electrical contact at a first side of the EIC facing the first side of the PIC; and
attaching the EIC to the PIC by stacking the EIC on the first side of the PIC with the first side of the EIC facing the first side of the PIC, electrically connecting the electrical contact at the first side of the EIC with the electrical contact at the first side of the PIC.
18. The method of claim 17 , wherein the electrical contact on the first side of the EIC is electrically connected to the electrical contact at the first side of the PIC with a copper pillar.
19. The method of claim 17 , further comprising filling a gap between the first side of the EIC and the first side of the PIC with a molding compound.
20. The method of claim 17 , further comprising electrically connecting the electrical contact at the second side of the PIC to ground.
21. The method of claim 17 , further comprising electrically connecting the electrical contact at the second side of the PIC to a variable direct current (DC) voltage source.