Quantum computing die assembly with thru-silicon vias and connected logic circuit
Techniques disclosed herein relate to devices that each include one or more photonic integrated circuits and/or one or more electronic integrated circuits. In one embodiment, a device includes a silicon substrate, a die stack bonded (e.g., fusion-bonded) on the silicon substrate, and a printed circuit board (PCB) bonded on the silicon substrate, where the PCB is electrically coupled to the die stack. The die stack includes a photonic integrated circuit (PIC) that includes a photonic integrated circuit, and an electronic integrated circuit (EIC) die that includes an electronic integrated circuit, where the EIC die and the PIC die are bonded face-to-face (e.g., by fusion bonding or hybrid bonding) such that the photonic integrated circuit and the electronic integrated circuit face each other. In some embodiments, the device also includes a plurality of optical fibers coupled to the photonic integrated circuit.
1. A device comprising:
a first die including a first circuit; and
a second die attached to the first die and including:
a second circuit including an electronic logic circuit that is electrically coupled to the first circuit; and
at least one electrically conductive via extending through the second die and electrically coupled to the electronic logic circuit.
2. The device of claim 1 , wherein the first die is a silicon-based photonic die and the first circuit includes a photon detector that is electrically coupled to the electronic logic circuit.
3. The device of claim 2 , wherein the photon detector is configured to detect single photons functioning as qubits in a quantum computing circuit.
4. The device of claim 1 , wherein the at least one electrically conductive via is a through silicon via (TSV) that electrically couples the electronic logic circuit to an external circuit.
5. The device of claim 1 , wherein the at least one electrically conductive via is a through silicon via (TSV) that is electrically coupled to an I/O terminal at an exterior surface of the second die.
6. The device of claim 5 , wherein the I/O terminal is a bonding pad that is coupled to an external circuit through one or more wirebonds.
7. The device of claim 1 , wherein the first die has a front surface opposite a back surface and second die has top surface opposite a bottom surface, wherein the back surface of the first die is attached to the top surface of the second die.
8. The device of claim 7 , wherein the first circuit is positioned at the back surface and the second circuit is positioned at the top surface, and wherein the first die and the second die are attached face-to-face such that the first circuit and the second circuit are proximate each other.
9. The device of claim 1 , wherein the first die is attached to a silicon wafer.
10. The device of claim 9 , wherein the first die is fusion bonded to the silicon wafer.
11. The device of claim 10 , wherein a circuit board is attached to the silicon wafer proximate the device and is electrically coupled to the first die.
12. The device of claim 11 , wherein the circuit board includes electrical connections coupled to the at least one electrically conductive via.
13. The device of claim 1 , wherein the first die includes a photodetector and an optical switch, wherein the photodetector is coupled to the electronic logic circuit and wherein in response to detecting a photon, the photodetector transmits a signal to the electronic logic circuit.
14. The device of claim 13 , wherein in response to receiving the signal, the electronic logic circuit controls the optical switch.
15. The device of claim 1 , wherein the second die includes a redistribution layer and a front surface of the redistribution layer includes one or more bonding pads.
16. The device of claim 1 , wherein the first die is fusion bonded to the second die.
17. The device of claim 1 , wherein the first die is hybrid bonded to the second die.
18. The device of claim 1 , wherein the first die is coupled to one or more optical fibers.
19. The device of claim 1 , wherein the first die receives electrical power through the at least one electrically conductive via.
20. The device of claim 1 , wherein first die and the second die are configured to operate in a cryogenic environment.