Hybrid bonding with photonic integrated circuits for high bandwidth reticle stitching of reticle sized integrated circuit dies
Embodiments of a microelectronic assembly comprise: a plurality of microelectronic sub-assemblies arranged in an array; and a plurality of photonic integrated circuit (PIC) dies, each PIC die having waveguides. Adjacent microelectronic sub-assemblies are coupled to one of the PIC dies by interconnects such that any one PIC die is coupled to more than two adjacent microelectronic sub-assemblies, and the microelectronic sub-assemblies coupled to each PIC die in the plurality of PIC dies are communicatively coupled by the waveguides in the PIC die. Each microelectronic sub-assembly comprises: an interposer integrated circuit (IC) die comprising one or more electrical controller circuit proximate to at least one edge of the interposer IC die; a first plurality of IC dies coupled to a first surface of the interposer IC die; and a second plurality of IC dies coupled to an opposing second surface of the interposer IC die.
1 . A microelectronic assembly, comprising:
an array of microelectronic sub-assemblies; and
a photonic integrated circuit (PIC) dies coupled to two or more microelectronic sub-assemblies of the array,
wherein an individual microelectronic sub-assembly of the array includes:
an interposer,
a first integrated circuit (IC) die coupled to a first side of the interposer,
a second IC die coupled to a second side of the interposer,
one of the first side and the second side is a top side and another one of the first side and the second side is a bottom side, and
the bottom side faces away from the top side.
2 . The microelectronic assembly of claim 1 , wherein:
the interposer includes one or more electrical controller circuits proximate to at least one edge of the interposer.
3 . The microelectronic assembly of claim 1 , wherein:
the individual microelectronic sub-assembly further includes a third IC die in a stack of IC dies coupled to the first side of the interposer,
the stack of IC dies further includes the first IC die,
one of the first IC die and the second IC die includes a cache memory circuit, and
another one of the first IC die and the second IC die includes a compute circuit.
4 . The microelectronic assembly of claim 1 , wherein the second IC die includes at least one of: a dynamic random access memory (DRAM) circuit, a physical layer interface (PHY) circuit, or an input/output (IO) circuit.
5 . The microelectronic assembly of claim 1 , wherein the interposer includes conductive pathways between the first IC die and the second IC die.
6 . The microelectronic assembly of claim 1 , wherein:
the interposer includes an electrical controller circuit conductively coupled to thePIC die, and
the electrical controller circuit is to aggregate electrical signals from the first IC die and the second IC die and transmit the electrical signals to the PIC die.
7 . The microelectronic assembly of claim 1 , wherein:
a gap is present between adjacent microelectronic sub-assemblies of the array, and the gap is approximately between 40 micrometers and 10 millimeters.
8 . The microelectronic assembly of claim 1 , wherein the PIC die comprises waveguides in more than one layer.
9 . A process of fabricating a microelectronic assembly, the process comprising:
placing a plurality of microelectronic sub-assemblies adjacent to each other such that the microelectronic sub-assemblies are coplanar and do not touch each other; and
coupling a photonic integrated circuit (PIC) die with two or more of the microelectronic sub-assemblies,
wherein an individual microelectronic sub-assembly of the microelectronic sub-assemblies includes:
an interposer,
a first plurality of integrated circuit (IC) dies coupled to a first surface of the interposer, and
a second plurality of IC dies coupled to a second surface of the interposer, the second surface being opposite the first surface.
10 . The process of claim 9 , wherein the PIC die comprises a plurality of waveguides in different layers of a dielectric material.
11 . The process of claim 10 , wherein the dielectric material has a different refractive index than the waveguides to a range of bandwidth of electromagnetic signals to be generated or transmitted by the PIC die.
12 . The process of claim 9 , further comprising coupling the microelectronic sub-assemblies with a package substrate by second-level interconnects.
13 . The process of claim 9 , wherein coupling the PIC die with two or more of the microelectronic sub-assemblies comprises forming hybrid bonds comprising metal-metal bonds and dielectric-dielectric bonds between the PIC die and the two or more of the microelectronic sub-assemblies.
14 . A microelectronic assembly, comprising:
microelectronic sub-assemblies arranged in an array; and
a photonic integrated circuit (PIC) die coupled to two or more of the microelectronic sub-assemblies,
wherein an individual microelectronic sub-assembly of the microelectronic sub-assemblies includes:
an interposer,
a first plurality of integrated circuit (IC) dies coupled to a first surface of the interposer, and
a second plurality of IC dies coupled to a second surface of the interposer, the second surface being opposite the first surface.
15 . The microelectronic assembly of claim 14 , wherein the interposer includes an electrical controller circuit proximate to an edge of the interposer.
16 . The microelectronic assembly of claim 15 , wherein the edge of the interposer is an edge that is closest to the PIC die.
17 . The microelectronic assembly of claim 16 , wherein:
the electrical controller circuit is a first electrical controller circuit,
the edge of the interposer is a first edge of the interposer, and
the interposer further includes a second electrical controller circuit proximate to a second edge of the interposer.
18 . The microelectronic assembly of claim 17 , wherein the second edge of the interposer is opposite the first edge of the interposer.
19 . The microelectronic assembly of claim 14 , wherein the microelectronic assemblies are coplanar and wherein adjacent microelectronic assemblies are spaced apart from each other by a gap.
20 . The microelectronic assembly of claim 14 , wherein the PIC die is coupled to the two or more of the microelectronic sub-assemblies by interconnects having a pitch of less than 10 micrometers between adjacent interconnects.