Integrated circuits including network interface controllers for data transfers assisted by software and related methods
A network interface controller (NIC) circuit may control data transfers between a network interface and a memory interface circuit. The NIC circuit receives data packets on the network interface and determines whether a packet type of a data packet corresponds to one of a first plurality of operations or a second plurality of operations. For data packets that correspond to one of the first plurality of operations, the NIC circuit controls the memory interface circuit according to the packet type and for data packets that correspond to one of the second plurality of operations, the NIC sends a notification to a processor circuit in the IC to execute software instructions to control the memory interface circuit according to the packet type. The NIC circuit quickly processes data packets corresponding to the first plurality of operations without software involvement but relies on software assistance for the second plurality of operations.
1 . An integrated circuit (IC), comprising:
a network interface controller (NIC) circuit coupled to a network interface;
a memory interface circuit coupled to a memory interface; and
at least one processor circuit;
wherein:
the NIC circuit is configured to:
receive a first data packet on the network interface;
determine a packet type of the first data packet;
in response to determining that the first data packet comprises a first packet type corresponding to a first operation of a first plurality of operations, control the memory interface circuit according to the first packet type; and
in response to determining that the first data packet comprises a second packet type corresponding to a second plurality of operations, send a notification to the at least one processor circuit to process the first data packet; and
the at least one processor circuit is configured to, in response to the notification, execute software instructions to control the memory interface circuit according to the second packet type.
2 . The IC of claim 1 , wherein the first operation of the first plurality of operations comprises a first transfer of first data from a payload of the first data packet to a system memory coupled to the memory interface.
3 . The IC of claim 2 , the IC further comprising:
an on-chip memory;
a packet receiver configured to store the first data packet in the on-chip memory; and
an address translation table;
wherein the NIC circuit is further configured to:
access the address translation table to determine a first physical address in the system memory corresponding to a first virtual address received in the first data packet; and
control the memory interface circuit to transfer the first data from the on-chip memory to the first physical address in the system memory.
4 . The IC of claim 1 , wherein:
the first data packet is received on the network interface based on a connection established according to an interface protocol; and
the NIC circuit is further configured to send a notification to the at least one processor circuit to send an acknowledgment of the first data packet on the network interface.
5 . The IC of claim 4 , wherein:
the at least one processor circuit is further configured to receive the notification; and
execute software instructions that cause the acknowledgment to be sent on the network interface according to the interface protocol.
6 . The IC of claim 4 , the NIC circuit further configured to:
in response to identifying an error associated with the first data packet, send a notification to the at least one processor circuit to execute software instructions to respond to the error according to the interface protocol.
7 . The IC of claim 4 , wherein:
the at least one processor circuit is further configured to execute software instructions to cause the connection to terminate according to the interface protocol.
8 . The IC of claim 4 , wherein:
the interface protocol on the network interface comprises remote direct memory access (RDMA) on converged Ethernet (RoCE); and
the first data packet comprises an RDMA message.
9 . The IC of claim 3 , wherein:
the second plurality of operations comprises a transfer of first data from the payload of the first data packet;
the NIC circuit is further configured to inform the at least one processor circuit of a first address of the first data in the on-chip memory; and
the at least one processor circuit is configured to:
control transfer of the first data from the on-chip memory to the memory interface circuit;
access the address translation table to translate the first virtual address in the first data packet to the first physical address in the system memory; and
provide the first physical address to the memory interface circuit for storing the first data.
10 . The IC of claim 9 , wherein:
the at least one processor circuit is further configured to execute software instructions to configure an address of a receive queue for the first data packet in the on-chip memory; and
the packet receiver is further configured to store the first data in the receive queue.
11 . The IC of claim 3 , wherein:
the at least one processor circuit is further configured to execute software instructions to configure the address translation table to associate the first physical address to the first virtual address of the first data.
12 . The IC of claim 10 , wherein:
the at least one processor circuit is further configured to execute software instructions to control the memory interface circuit to transfer the first data from the receive queue in the on-chip memory to the first physical address in the system memory.
13 . A method in an integrated circuit (IC), the method comprising:
receiving, in a network interface controller (NIC) circuit, a first data packet on a network interface;
determining a packet type of the first data packet;
in response to determining that the first data packet comprises a first packet type corresponding to a first operation of a first plurality of operations, controlling a memory interface circuit according to the first packet type;
in response to determining that the first data packet comprises a second packet type corresponding to a second plurality of operations, sending a notification to at least one processor circuit to execute software instructions to process the first data packet; and
in response to the notification, controlling, by the at least one processor circuit based on software instructions, the memory interface circuit to transfer data according to the second packet type.
14 . The method of claim 13 , wherein the first operation of the first plurality of operations comprises a first transfer of first data from a payload of the first data packet to a system memory coupled to a memory interface.
15 . The method of claim 14 , further comprising:
accessing an address translation table to determine a first physical address in the system memory corresponding to a first virtual address received in the first data packet; and
controlling the memory interface circuit to transfer the first data from an on-chip memory to the first physical address in the system memory.
16 . The method of claim 13 , further comprising:
receiving the first data packet on the network interface based on a connection established according to an interface protocol; and
sending a notification, by the NIC circuit, to the at least one processor circuit to send an acknowledgment of the first data packet on the network interface.
17 . The method of claim 16 , further comprising:
receiving the notification in the at least one processor circuit; and
executing software instructions to cause the acknowledgment to be sent on the network interface according to the interface protocol.
18 . The method of claim 16 , the NIC circuit further configured to:
identify, by the NIC circuit, an error associated with the first data packet; and
send a notification to the at least one processor circuit to execute software instructions to respond to the error according to the interface protocol.
19 . The method of claim 16 , further comprising:
executing, in the at least one processor circuit, software instructions to terminate the connection according to the interface protocol.
20 . The method of claim 16 , wherein:
the interface protocol on the network interface comprises remote direct memory access (RDMA) on converged Ethernet (RoCE); and
the first data packet comprises an RDMA message.
21 . The method of claim 15 , wherein the second plurality of operations comprises a transfer of the first data from the payload of the first data packet, the method further comprising:
providing, by the NIC circuit, the at least one processor circuit a first address of the first data packet in the on-chip memory;
controlling, by the at least one processor circuit, the transfer of the first data from the on-chip memory to the memory interface circuit;
accessing, by the at least one processor circuit, the address translation table to translate the first virtual address in the first data packet to the first physical address in the system memory; and
providing, by the at least one processor circuit, the first physical address to the memory interface circuit to store the first data.
22 . The method of claim 15 , further comprising:
executing, in the at least one processor circuit, software instructions to determine an address of a receive queue for the first data packet in the on-chip memory; and
storing the first data in the receive queue.
23 . The method of claim 15 , further comprising:
executing, in the at least one processor circuit, software instructions to configure the address translation table to associate the first physical address to the first virtual address of the first data.
24 . The method of claim 22 , wherein:
the at least one processor circuit is further configured to execute software instructions to control the memory interface circuit to transfer the first data from the receive queue in the on-chip memory to the first physical address in the system memory.