Display panel having dual-mode pixel circuit, and display device
View Patent ↗The present disclosure provides a display panel and a display device. A pixel circuit in the display panel is operable in any one of the first mode and the second mode. A duration Ld 1 of a non-light-emitting period of a data writing frame in the first mode, a duration Lm 1 of the non-light-emitting period of a holding frame in the first mode, a duration Ld 2 of the non-light-emitting period of the data writing frame in the second mode, and a duration of the non-light-emitting period of the holding frame in the second mode are flexibly adjusted according to a relationship of Ld 1 >Ld 2 , and/or, Lm 1 >Lm 2 , and durations of the non-light-emitting periods in the data writing frame and the holding frame are optimized to ensure good display effects of the display panel in different modes.
1 . A display panel, comprising:
a pixel circuit and a light-emitting element, wherein
the pixel circuit comprises a driving module and a signal conditioning module;
the driving module comprises a driving transistor;
a frame time of the display panel comprises a non-light-emitting period and a light-emitting period, the non-light-emitting period comprises a signal conditioning phase, and the signal conditioning module is configured to provide a preset signal for the driving transistor in the signal conditioning phase;
an image refresh frame of the pixel circuit comprises a data writing frame and a holding frame, the data writing frame comprises p signal conditioning phases, p≥1, and/or, the holding frame comprises q signal conditioning phases, q≥0;
the pixel circuit is operable in any one of a first mode and a second mode;
in the first mode, a duration of the non-light-emitting period of the data writing frame is Ld 1 , and a duration of the non-light-emitting period of the holding frame is Lm 1 ;
in the second mode, a duration of the non-light-emitting period of the data writing frame is Ld 2 , and a duration of the non-light-emitting period of the holding frame is Lm 2 ;
wherein, Ld 1 >Ld 2 , and/or, Lm 1 >Lm 2 ;
wherein
in the first mode, in the data writing frame, a total duration of the p signal conditioning phases is Wd 1 , and in the holding frame, a total duration of the q signal conditioning phase is Wm 1 ; in the second mode, in the data writing frame, a total duration of the p signal conditioning phase is Wd 2 , and in the holding frame, a total duration of the q signal conditioning phase is Wm 2 ; and Wd 1 /Ld 1 ≠Wm 1 /Lm 1 and/or Wd 2 /Ld 2 ≠Wm 2 /Lm 2 ; or
in the first mode, in the data writing frame, a duration of a time period between a start of the non-light-emitting period and a start of a first signal conditioning phase is Tda 1 , and in the holding frame, a duration of a time period between the start of the non-light-emitting period and the start of the first signal conditioning phase is Tma 1 ; in the second mode, in the data writing frame, the duration of the time period between the start of the non-light-emitting period and the start of the first signal conditioning phase is Tda 2 , and in the holding frame, the duration of the time period between the start of the non-light-emitting period and the start of the first signal conditioning phase is Tma 2 ; and Tda 1 ≠Tma 1 and/or Tad 2 ≠Tma 2 ; or
in the first mode, in the data writing frame, a duration of a time period between an end of a last signal conditioning phase and an end of the non-light-emitting period is Tdb 1 , and in the holding frame, a duration of a time period between the end of the last signal conditioning phase and the end of the non-light-emitting period is Tmb 1 ; in the second mode, in the data writing frame, a duration of the time period between the end of the last signal conditioning phase and the end of the non-light-emitting period Tdb 2 , and int the holding frame, a duration of the time period between the end of the last signal conditioning phase and the end of the non-light-emitting period is Tmb 2 ; and Tdb 1 ≠Tmb 1 and/or Tdb 2 ≠Tmb 2 .
2 . The display panel according to claim 1 , wherein in the first mode, a luminance of the display panel is B 1 , and in the second mode, a luminance of the display panel is B 2 , and B 1 <B 2 .
3 . The display panel according to claim 1 , wherein in the first mode, a frame frequency of the image refresh frame of the display panel is Fv 1 , and in the second mode, a frame frequency of the image refresh frame of the display panel is Fv 2 , and Fv 1 <Fv 2 .
4 . The display panel according to claim 1 , wherein in the first mode, a duration of the image refresh frame of the display panel is S 1 , and in the second mode, a duration of the image refresh frame of the display panel is S 2 , S 1 >S 2 .
5 . The display panel according to claim 1 , further comprising a first pixel circuit and a second pixel circuit, during at least a part of operation of the display panel, the first pixel circuit operates in the first mode, and the second pixel circuit operates in the second mode.
6 . The display panel according to claim 5 , wherein a data refresh frequency of the first pixel circuit is Fs 1 , and a data refresh frequency of the second pixel circuit is Fs 2 , and Fs 1 ≠Fs 2 .
7 . The display panel according to claim 5 , further comprising a first display area and a second display area, wherein the first pixel circuit is located in the first display area, and the second pixel circuit is located in the second display area.
8 . The display panel according to claim 1 , wherein an operation time of the display panel comprises a first time period and a second time period, in the first time period, the pixel circuit operates in the first mode, and in the second time period, the pixel circuit operates in the second mode.
9 . The display panel according to claim 1 , wherein Ld 1 =Lm 1 , and/or, Ld 2 =Lm 2 .
10 . The display panel according to claim 1 , wherein Ld 1 ≠Lm 1 , and/or, Ld 2 ≠Lm 2 .
11 . The display panel according to claim 10 , wherein Ld 1 >Lm 1 , and/or, Ld 2 >Lm 2 .
12 . The display panel according to claim 10 , wherein Ld 1 <Lm 1 , and/or, Ld 2 <Lm 2 .
13 . The display panel according to claim 1 , wherein Wd 1 /Ld 1 >Wm 1 /Lm 1 ; and/or, Wd 2 /Ld 2 >Wm 2 /Lm 2 .
14 . The display panel according to claim 1 , wherein Wd 1 /Ld 1 <Wm/Lm 1 ; and/or, Wd 2 /Ld 2 <Wm 2 /Lm 2 .
15 . The display panel according to claim 1 , wherein Wd 1 /Ld 1 <Wd 2 /Ld 2 ; and/or, Wm 1 /Lm 1 =Wm 2 /Lm 2 .
16 . The display panel according to claim 1 , wherein Wd 1 /Ld 1 #Wd 2 /Ld 2 ; and/or, Wm 1 /Lm 1 Wm 2 /Lm 2 .
17 . The display panel according to claim 16 , wherein Wd 1 /Ld 1 <Wd 2 /Ld 2 ; and/or, Wm 1 /Lm 1 <Wm 2 /Lm 2 .
18 . The display panel according to claim 1 , wherein the signal conditioning module is a data writing module, and the preset signal is a data signal; the data writing module is connected to a first electrode of the driving transistor, and in the signal conditioning phase, the data writing module is turned on to provide the data signal for the driving transistor; or,
wherein the signal conditioning module is a reset module, and the preset signal is a reset signal, the reset module is connected to a gate electrode of the driving transistor, and in the signal conditioning phase, the reset module is turned on to provide a reset signal for the driving transistor; or,
wherein the signal conditioning module is a bias conditioning module, and the preset signal is a bias conditioning signal, the bias conditioning module is connected to a first electrode or a second electrode of the driving transistor, and in the signal conditioning phase, the bias conditioning module is turned on to provide the bias conditioning signal for the driving transistor.
19 . A display device, comprising:
a display panel, wherein
the display panel comprises a pixel circuit and a light-emitting element;
the pixel circuit comprises a driving module and a signal conditioning module;
the driving module comprises a driving transistor;
a frame time of the display panel comprises a non-light-emitting period and a light-emitting period, the non-light-emitting period comprises a signal conditioning phase, and the signal conditioning module is configured to provide a preset signal for the driving transistor in the signal conditioning phase;
an image refresh frame of the pixel circuit comprises a data writing frame and a holding frame, the data writing frame comprises p signal conditioning phases, p≥1, and/or, the holding frame comprises q signal conditioning phases, q≥0;
the pixel circuit is operable in any one of a first mode and a second mode;
in the first mode, a duration of the non-light-emitting period of the data writing frame is Ld 1 , and a duration of the non-light-emitting period of the holding frame is Lm 1 ;
in the second mode, a duration of the non-light-emitting period of the data writing frame is Ld 2 , and a duration of the non-light-emitting period of the holding frame is Lm 2 ;
wherein, Ld 1 >Ld 2 , and/or, Lm 1 >Lm 2 ;
wherein
in the first mode, in the data writing frame, a total duration of the p signal conditioning phases is Wd 1 , and in the holding frame, a total duration of the q signal conditioning phase is Wm 1 ; in the second mode, in the data writing frame, a total duration of the p signal conditioning phase is Wd 2 , and in the holding frame, a total duration of the q signal conditioning, phase is Wm 2 ; and Wd 1 /Ld 1 ≠Wm 1 /Lm 1 and/or Wd 2 /Ld 2 ≠Wm 2 /Lm 2 ; or
in the first mode, in the data writing frame, a duration of a time period between a start of the non-light-emitting period and a start of a first signal conditioning phase is Tda 1 , and in the holding frame, a duration of a time period between the start of the non-light-emitting period and the start of the first signal conditioning phase is Tma 1 ; in the second mode, in the data writing frame, the duration of the time period between the start of the non-light-emitting period and the start of the first signal conditioning phase is Tda 1 , and in the holding frame, the duration of the time period between the start of the non-light-emitting period and the start of the first signal conditioning phase is Tma 2 ; and Tda 1 ≠Tma 1 and/or Tad 2 ≠Tma 2 ; or
in the first mode, in the data writing frame, a duration of a time period between an end of a last signal conditioning phase and an end of the non-light-emitting period is Tdb 1 , and in the holding frame, a duration of a time period between the end of the last signal conditioning phase and the end of the non-light-emitting period is Tmb 1 ; in the second mode, in the data writing frame, a duration of the time period between the end of the last signal conditioning phase and the end of the non-light-emitting period is Tdb 2 , and in the holding frame, a duration of the time period between the end of the last signal conditioning phase and the end of the non-light-emitting period is Tmb 2 ; and Tdb 1 ≠Tmb 1 and/or Tdb 2 ≠Tmb 2 .