IP Library Granted Patent US 12,608,453
Granted Patent B2
US 12,608,453 · App. 18/759,353 · Granted Apr 21, 2026

Method and system for watermarking a USB PD protocol hardware sub-system

Inventors: Shubham Paliwal (Uttar Pradesh, IN); Rakesh Kumar Polasa (Karnataka, IN); Vishnu Mohan Pusuluri (Karnataka, IN); Venugopal Jennarapu (Karnataka, IN)
Assignee: SILICONCH SYSTEMS PRIVATE LIMITED
G06F21/16G06F1/3215G06F21/44
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Quick Facts
Patent No.
US 12,608,453
App. No.
18/759,353
Granted
Apr 21, 2026
Kind
B2
Abstract

A system for watermarking a USB Type-C and PD protocol hardware sub-system existing as a part of a SOC/IC system includes a tester to generate a watermarking signal, a device under test (DUT), wherein the DUT is configured with a USB Type-C port with power delivery implementation and including a hardware subsystem configured for watermarking the DUT and transmit a response signal upon receipt of the watermarking signal from the tester. The tester includes a controller including one or more processors that execute a set of executable instructions that are stored in a memory, upon which execution, the processor causes the controller to generate the watermarking signal, the watermarking signal comprises a custom signal and a custom packet associated with a configured custom signal stored in a data buffer that is associated with the SOC/IC system, and transmit the watermarking signal on one or more configuration channel (CC) lines.

Claims (8)

1 . A hardware subsystem operatively coupled to a device under test (DUT), said hardware subsystem comprising:

a watermarking signal detection circuit comprising a multiplexer structure, a look-up table storing key-value pairs mapping combinations of K-codes to predefined packets, and control logic, wherein the watermarking signal detection circuit is configured to:

detect a watermarking signal transmitted by a tester on a configuration channel (CC) lines coupled to a Type-C port of a Universal Serial Bus (USB) Type-C and Power Delivery (PD) protocol associated with the hardware subsystem, said tester configured to test whether the DUT is watermarked or not, wherein the watermarking signal comprises a custom signaling comprising a combination of K-Codes, other than Start of Packet (SOP) ordered sets defined in the USB Power Delivery Specification;

automatically assume control via the multiplexer structure to enable direct communication between the watermarking signal detection circuit and a USB Type-C and PD stack and a bus interface, bypassing a System on Chip/Integrated Circuit (SOC/IC) microcontroller associated with the hardware subsystem;

respond with a response signal, said response signal comprising a pre-defined packet having a vendor identity and a secret code corresponding to the combination of K-codes received;

wherein the watermarking signal comprises the combination of K-codes;

transmit the response signal through a buffer in an existing USB Type-C and PD stack, wherein the response signal is fetched through a key-value mechanism comprising a unique code corresponding to the combination of K-codes in the watermarking signal; and

relinquishes control via the multiplexer structure to restore communication between the microcontroller (MCU) and the bus interface and the USB Type-C and PD stack, the microcontroller (MCU) operatively coupled to the DUT once a transmission of the response signal is complete.

Assignments (2)
MERGER Recorded Apr 22, 2026
From: SILICONCH SYSTEMS PRIVATE LIMITED
To: L&T SEMICONDUCTOR TECHNOLOGIES LIMITED
Reel/Frame 075446/0549 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 28, 2024
From: PALIWAL, SHUBHAM; POLASA, RAKESH KUMAR; PUSULURI, VISHNU MOHAN; JENNARAPU, VENUGOPAL
To: SILICONCH SYSTEMS PRIVATE LIMITED
Reel/Frame 067876/0033 →
Priority Claims (1)
IN 202241008679 · Feb 18, 2022 · national
Continuity (2)
Division 17857298 · Jul 5, 2022
Related Publication 20240354381A1 · Oct 24, 2024
References Cited (8)
US 9081957B2 · Roden, III · 2015 [cited by examiner]
US 20070220263A1 · Ziener · 2007 [cited by examiner]
US 20170370964A1 · Chen · 2017 [cited by examiner]
US 20180181371A1 · Chellappan · 2018 [cited by examiner]
US 20220244309A1 · Sirisha · 2022 [cited by examiner]
EP 1835425B1 · 2009 [cited by applicant]
Universal Serial Bus Type-C Cable and Connector Specification Release 2.0, USB 3.0 Promoter Group, Aug. 2019 (373 pages). [cited by applicant]
Universal Serial Bus Power Delivery Specification, Revision 3.0, Version 2.0, Aug. 29, 2019 (657 pages). [cited by applicant]