IP Library Granted Patent US 12,731,653
Granted Patent B2
US 12,731,653 · App. 18/762,272 · Granted Sep 8, 2026

Non-volatile memory system and data recover read operation method thereof

Inventors: JunHo Kim (Suwon-si, KR); Sangjin Yoo (Suwon-si, KR); Kwangwoo Lee (Suwon-si, KR); Jeongwoo Lee (Suwon-si, KR); Heewon Lee (Suwon-si, KR)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
G11C16/349G11C16/26G11C29/52
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Quick Facts
Patent No.
US 12,731,653
App. No.
18/762,272
Granted
Sep 8, 2026
Kind
B2
Abstract

A data recover read (DRR) operation method of a nonvolatile memory system includes: performing a first read operation on adjacent memory cells, which are connected to an adjacent wordline adjacent to a target wordline, based on a first specific read level; obtaining a cell count value for the adjacent wordline; determining offset values for a normal read level of target memory cells, which are connected to the target wordline, based on the cell count value for the adjacent wordline; and performing a second read operation on the target memory cells, based on the determined offset values and a result of the first read operation.

Claims (45)

1 . A data recover read (DRR) operation method of a nonvolatile memory system, the DRR operation method comprising:

performing a first read operation on adjacent memory cells, which are connected to an adjacent wordline adjacent to a target wordline, based on a first specific read level;

obtaining a cell count value for the adjacent wordline;

determining offset values for a normal read level of target memory cells, which are connected to the target wordline, by using at least one of an offset table or an algorithm, which defines an optimal offset value based on the cell count value for the adjacent wordline, as a first variable, and further based on a value of additional information, as a second variable; and

performing a second read operation on the target memory cells, based on the determined offset values and a result of the first read operation,

wherein the additional information comprises at least one of a program/erase (P/E) cycle of the target memory cells, temperature of the target memory cells, or a location of the target wordline, and

wherein the offset table includes a plurality of predetermined offset values that respectively match with preset values of the cell count value and at least one of preset values of the P/E cycle of the target memory cells, preset values of the temperature of the target memory cells, or preset values of the location of the target wordline.

2 . The DRR operation method of claim 1 , wherein the first specific read level is a normal read level corresponding to a specific program state, among a plurality of program states, of the adjacent memory cells.

3 . The DRR operation method of claim 1 , wherein the cell count value for the adjacent wordline comprises at least one of an ON-cell count value related to a number of turned-on adjacent memory cells, an OFF-cell count value related to a number of turned-off adjacent memory cells, or a difference value between the ON-cell count value and the OFF-cell count value.

4 . The DRR operation method of claim 1 , wherein the determining the offset values comprises determining the offset values based on the offset table, the offset table comprising optimal offset values that respectively match cell count values and values of the additional information.

5 . The DRR operation method of claim 1 , wherein the determining the offset values comprises determining the offset values based on the algorithm, and

wherein the algorithm is derived through machine learning based on training data, the training data comprising the cell count value, the value of the additional information, and the optimal offset value.

6 . The DRR operation method of claim 1 , wherein each of the target memory cells belongs to a single group, among a plurality of groups, based on a program state of an adjacent memory cell sharing a bitline with a corresponding target memory cell, and

wherein the determined offset values correspond to the plurality of groups, respectively.

7 . The DRR operation method of claim 6 , wherein the plurality of groups belong to a single DRR group, which is selected based on the cell count value for the adjacent wordline, among a plurality of DRR groups including different numbers of groups.

8 . The DRR operation method of claim 7 , wherein the plurality of DRR groups comprises a first DRR group and a second DRR group, the first DRR group comprising two groups distinguished with each other with respect to the first specific read level, and the second DRR group comprising four groups distinguished with one another with respect to three specific read levels, and

wherein the three specific read levels comprise the first specific read level, a second specific read level lower than the first specific read level, and a third specific read level higher than the first specific read level.

9 . The DRR operation method of claim 8 , further comprising, based on the second DRR group being selected:

performing a third read operation based on the second specific read level on the adjacent memory cells and performing a fourth read operation on the adjacent memory cells based on the third specific read level on the adjacent memory cells.

10 . The DRR operation method of claim 1 , wherein the performing the second read operation comprises:

performing a read operation on the target memory cells based on each of the determined offset values; and

combining results of read operations performed based on the each of the determined offset values, based on the result of the first read operation.

11 . The DRR operation method of claim 1 , wherein the adjacent wordline is a wordline programmed in a sequence next to the target wordline during a program operation, among wordlines adjacent to the target wordline.

12 . The DRR operation method of claim 1 , wherein the DRR operation method is performed based on an uncorrectable error correction code (UECC) being generated in a normal read operation performed on the target memory cells.

13 . A nonvolatile memory system comprising:

a nonvolatile memory device comprising target memory cells, connected to a target wordline, and adjacent memory cells connected to an adjacent wordline adjacent to the target wordline; and

a controller configured to control an operation of the nonvolatile memory device,

wherein the nonvolatile memory device is configured to perform a first read operation on the adjacent memory cells based on a specific read level and configured to obtain a cell count value for the adjacent wordline,

wherein the controller is configured to determine offset values for calibrating a normal read level of the target memory cells, by using at least one of an offset table or an algorithm, which defines an optimal offset value based on the cell count value for the adjacent wordline, as a first variable, and further based on a value of additional information, as a second variable, and configured to control the nonvolatile memory device to perform a second read operation on the target memory cells based on the determined offset values and a result of the first read operation,

wherein the additional information comprises at least one of a program/erase (P/E) cycle of the target memory cells, temperature of the target memory cells, or a location of the target wordline, and

wherein the offset table includes a plurality of predetermined offset values that respectively match with preset values of the cell count value and at least one of preset values of the P/E cycle of the target memory cells, preset values of the temperature of the target memory cells, or preset values of the location of the target wordline.

14 . The nonvolatile memory system of claim 13 , wherein the specific read level is a normal read level corresponding to a specific program state, among a plurality of program states of the adjacent memory cells, and

wherein the cell count value for the adjacent wordline comprises at least one of an ON-cell count value related to a number of turned-on adjacent memory cells, an OFF-cell count value related to a number of turned-off adjacent memory cells, or a difference value between the ON-cell count value and the OFF-cell count value.

15 . The nonvolatile memory system of claim 13 , wherein the controller is further configured to determine the offset values based on the offset table, the offset table comprising optimal offset values that respectively match cell count values and values of the additional information.

16 . The nonvolatile memory system of claim 13 , wherein the controller is further configured to determine the offset values based on the algorithm, and

wherein the algorithm is derived through machine learning based on training data, the training data comprising the cell count value, the value of the additional information, and the optimal offset value.

17 . The nonvolatile memory system of claim 13 , wherein each of the target memory cells belongs to a single group, among a plurality of groups, based on a program state of an adjacent memory cell sharing a bitline with a corresponding target memory cell, and

wherein the determined offset values correspond to the plurality of groups, respectively.

18 . A nonvolatile memory device comprising:

a memory cell array comprising target memory cells, connected to a target wordline, and adjacent memory cells connected to an adjacent wordline adjacent to the target wordline; and

a control logic configured to perform a first read operation based on a specific read level and configured to obtain a cell count value for the adjacent wordline,

wherein the control logic performs a second read operation on the target memory cells, based on offset values for calibrating a normal read level of target memory cells and a result of the first read operation,

wherein the offset values are determined by using at least one of an offset table or an algorithm, which defines an optimal offset value based on the cell count value for the adjacent wordline, as a first variable, and further based on a value of additional information, as a second variable,

wherein the additional information comprises at least one of a program/erase (P/E) cycle of the target memory cells, temperature of the target memory cells, or a location of the target wordline, and

wherein the offset table includes a plurality of predetermined offset values that respectively match with preset values of the cell count value and at least one of preset values of the P/E cycle of the target memory cells, preset values of the temperature of the target memory cells, or preset values of the location of the target wordline.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 2, 2024
From: KIM, JUNHO; YOO, SANGJIN; LEE, KWANGWOO; LEE, JEONGWOO; LEE, HEEWON
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 067899/0001 →
Priority Claims (1)
KR 10-2023-0128582 · Sep 25, 2023 · national
Continuity (1)
Related Publication 20250104784A1 · Mar 27, 2025
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