Driver circuit comprising a power stage, related half-bridge driver circuit, control circuit for an electronic converter, integrated circuit and method
A power stage includes parallel FETs including a reference FET. An input PWM signal has a switching period. A current sensor senses current flowing through the power stage during switch-on period. A first circuit generates a first PWM signal having a duty-cycle indicative of reference FET driving losses for a reference current. A second circuit generates a second PWM signal having a duty-cycle indicative of reference FET conduction losses for that reference current. The duty cycles of the first and second PWM signals are compared to generate a comparison signal. The reference current is changed until a logic state of the comparison signal changes. A respective enable signal for each FET is generated by comparing the reference current to the sensed current flowing through the power stage. A FET driver circuit generates a respective drive signal for each FET by combining the respective enable signal with the input PWM signal.
1 . A driver circuit, comprising:
a power stage comprising a plurality of FETs connected in parallel, wherein one of said plurality of FETs comprises a reference FET closed in response to application of a gate-source voltage;
an input configured to receive a Pulse-Width Modulated (PWM) signal with a given switching period, wherein said PWM signal is asserted for a switch-on period to control said power stage to be closed and de-asserted for a switch-off period to control said power stage to be opened;
a current sensor configured to provide a signal indicative of a current flowing through said power stage during said switch-on period;
a reference capacitance comprising a first scaled FET corresponding to a scaled version of said reference FET;
a reference resistance comprising a second scaled FET corresponding to another scaled version of said reference FET;
a first circuit configured to:
generate a ramp signal at said reference capacitance by connecting a gate terminal of said first scaled FET after a multiple of said given switching periods to ground and then applying a first current to the gate terminal of said first scaled FET, wherein said first current is proportional to a reference current; and
assert a first PWM signal in response to determining that a voltage at said reference capacitance is smaller than a reference voltage and de-assert said first PWM signal in response to determining that the voltage at said reference capacitance is greater than said reference voltage, wherein said reference voltage is proportional to said gate-source voltage;
a second circuit configured to:
apply a second current to a further capacitance when said PWM signal is asserted, wherein said second current is proportional to said reference current;
generate a third current by applying a voltage proportional to said gate-source voltage to said reference resistance;
apply said third current to said further capacitance when a second PWM signal is asserted, wherein said third current and said second current have opposite signs; and
assert said second PWM signal in response to a voltage at said further capacitance reaching an upper threshold and de-assert said second PWM signal in response to the voltage at said further capacitance reaching a lower threshold;
a duty-cycle comparison circuit configured to set a comparison signal to a first logic level in response to determining that a duty-cycle of said first PWM signal is greater than a duty-cycle of said second PWM signal and set the comparison signal to a second logic level in response to determining that the duty-cycle of said first PWM signal is smaller than the duty-cycle of said second PWM signal;
a control circuit configured to set said reference current to an initial value and then either increase or decrease said reference current until there is a change between the first and second logic levels of said comparison signal;
a comparison circuit configured to determine a respective enable signal for each FET of said plurality of FETs by comparing the value of said reference current in response to the change between the first and second logic levels of said comparison signal with said signal indicative of the current flowing through said power stage during said switch-on period; and
a FET driver circuit configured to generate for each FET of said plurality of FETs a respective drive signal by combining the respective enable signal with said PWM signal.
2 . The driver circuit of claim 1 , wherein said signal indicative of the current flowing through said power stage during said switch-on period is indicative of a Root-Mean-Square value of said current flowing through said power stage during said switch-on period.
3 . The driver circuit of claim 1 , wherein said signal indicative of the current flowing through said power stage during said switch-on period is indicative of a maximum value of said current flowing through said power stage during said switch-on period.
4 . The driver circuit of claim 1 , wherein said comparison circuit is further configured to determine a signal indicative of a partitioning value of said power stage by:
determining for each partitioning value of a plurality of partitioning values respective upper and lower threshold values as a function of said value of said reference current in response to the change between the first and second logic levels of said comparison signal; and
selecting one of said partitioning values by comparing said signal indicative of the current flowing through said power stage during said switch-on period with said upper and lower threshold values.
5 . The driver circuit of claim 4 , wherein each FET of said plurality of FETs has a respective partitioning factor and said comparison circuit is configured to:
determine said enable signals as a function of said partitioning factors of said plurality of FETs and a signal indicating said selected partitioning value.
6 . The driver circuit of claim 1 , further comprising a current digital-to-analog converter configured to generate said reference current as a function of a digital signal, and wherein said control circuit is configured to:
set said digital signal to an initial value; and
then either increase or decrease said digital signal until said change between the first and second logic levels of said comparison signal; and
then store said digital signal;
wherein said comparison circuit is configured to compare said stored digital signal with said signal indicative of the current flowing through said power stage during said switch-on period.
7 . The driver circuit of claim 1 , wherein said first circuit is configured to connect the gate terminal of said first scaled FET at the beginning of each switching period to ground.
8 . The driver circuit of claim 1 , wherein said duty-cycle comparison circuit comprises a differential current integrator, said duty cycle comparison configured to:
periodically reset said differential current integrator;
apply a first reference current to a first terminal of said differential current integrator when said first PWM signal is asserted;
apply a second reference current to a second terminal of said differential current integrator when said second PWM signal is asserted; and
generate said comparison signal as a function of the differential voltage at the output of said differential current integrator.
9 . The driver circuit of claim 1 , wherein said FET driver circuit is configured to generate for each FET of said plurality of FETs a respective drive signal by:
asserting the respective drive signal when said PWM signal is asserted and the respective enable signal indicates that the respective FET is enabled; and
de-asserting the respective drive signal when said PWM signal is de-asserted or the respective enable signal indicates that the respective FET is disabled.
10 . A half-bridge driver circuit, comprising:
a driver circuit according to claim 1 , wherein the power stage of said driver circuit is a low-side power stage comprising a plurality of low-side FETs connected between a switching node and a ground, wherein one of said plurality of low-side FETs represents said reference FET; wherein said input of said driver circuit is configured to receive a low-side PWM signal;
a high-side power stage comprising a plurality of high-side FETs connected between a supply voltage and said switching node; and
a further input configured to receive a high-side PWM signal with said given switching period, wherein said high-side PWM signal is asserted for a switch-on period in order to indicate that said high-side power stage should be closed and de-asserted for a switch-off period in order to indicate that said high-side power stage should be opened;
wherein the current sensor of said driver circuit is configured to provide a signal indicative of the current provided by said switching node;
wherein the second circuit of said driver circuit is configured to:
in a low-side mode, apply said second current to said further capacitance when said low-side PWM signal is asserted; and
in a high-side mode, apply said second current to said capacitance when the high-side PWM signal is asserted;
wherein the control circuit of said driver circuit is configured to:
in said low-side mode, set said reference current to an initial value and then either increase or decrease said reference current until the logic level of said comparison signal changes, and store a low-side value indicative of the value of said reference current when the logic level of said comparison signal changes, and
in said high-side mode, set said reference current to an initial value and then either increase or decrease said reference current until the logic level of said comparison signal changes, and store a high-side value indicative of the value of said reference current when the logic level of said comparison signal changes;
wherein the comparison circuit of the driver circuit is configured to determine for each FET of said plurality of low-side FETs a respective low-side enable signal by comparing the low-side value with said signal indicative of the current provided by said switching node;
wherein the half-bridge driver circuit comprises a further comparison circuit configured to determine for each FET of said plurality of high-side FETs a respective high-side enable signal by comparing the high-side value with said signal indicative of the current provided by said switching node;
wherein the FET driver circuit of said driver circuit is configured to generate for each FET of said plurality of low-side FETs a respective drive signal by combining a respective low-side enable signal with said low-side PWM signal; and
wherein the half-bridge driver circuit comprises a further FET driver circuit configured to generate for each FET of said plurality of high-side FETs a respective drive signal by combining a respective high-side enable signal with said high-side PWM signal.
11 . The half-bridge driver circuit according to claim 10 , wherein said further FET driver circuit comprises for each high-side enable signal a respective level-shifter circuit configured to generate a level-shifted version of the respective enable signal.
12 . An integrated circuit comprising the half-bridge driver circuit according to claim 10 .
13 . A control circuit for an electronic converter, comprising:
the half-bridge driver circuit according to claim 10 ; and
a PWM signal generator configured to generate said low-side PWM signal and said high-side PWM signal.
14 . An integrated circuit comprising the control circuit according to claim 13 .
15 . A control circuit for an electronic converter, comprising:
the driver circuit according to claim 1 ; and
a PWM signal generator configured to generate said PWM signal.
16 . An integrated circuit comprising the control circuit according to claim 15 .
17 . An integrated circuit comprising the driver circuit according to claim 1 .
18 . A driver circuit, comprising:
a power stage comprising a plurality of FETs connected in parallel, wherein one of said plurality of FETs comprises a reference FET;
a FET driver circuit configured to generate for each FET of said plurality of FETs a respective drive signal by combining a respective enable signal with a PWM signal;
a current sensor configured to sense current flowing through said power stage;
a reference capacitance;
a reference resistance;
a first circuit configured to apply a first current to said reference capacitance to generate a ramp signal and compare the ramp signal to a reference voltage to generate a first PWM signal;
a second circuit configured to source a second current to a further capacitance in response to assertion of the PWM signal and sink a third current from said further capacitance in response to a second PWM signal, wherein the second PWM is asserted in response to a voltage at said further capacitance reaching an upper threshold and deasserted in response to the voltage at said further capacitance reaching a lower threshold;
a duty-cycle comparison circuit configured to compare duty cycles of the first and second PWM signals to generate a comparison signal;
a control circuit configured to apply a change in a value of said reference current until said comparison signal changes logic state; and
a comparison circuit configured to generate the respective enable signals for said plurality of FETs in response to a comparison of the value of said reference current when the comparison signal changes logic state with the sensed current flowing through said power stage.
19 . The driver circuit according to claim 18 , wherein the sensed current flowing through said power stage is one of a Root-Mean-Square value of current flowing through said power stage or a maximum value of current flowing through said power stage.
20 . The driver circuit according to claim 18 , wherein each FET of said plurality of FETs has a respective partitioning factor and said comparison circuit is configured to determine said enable signals as a function of the partitioning factor a signal indicating a selected partitioning value.
21 . The driver circuit according to claim 18 , further comprising a current digital-to-analog converter configured to generate said reference current as a function of a digital signal.