Gate driver, display device including the same, and driving method of display device

1. A gate driver comprising:

a plurality of stages cascade-connected to each other through a carry signal line,

wherein the plurality of stages includes:

a first stage configured to receive a first clock signal and a start signal, and output a first gate signal and a first carry signal;

a J th stage configured to receive a J th clock signal and a J−1 th carry signal, and output a J th gate signal and a J th carry signal, wherein J is a positive integer that is greater than or equal to 2 and less than or equal to N; and

an N th stage configured to receive an N th clock signal and an N−1 th carry signal, and output an N th gate signal and an N th carry signal, wherein N is a natural number that is greater than or equal to 2, and

wherein each of the first stage, the J th stage, and the N th stage includes:

a clock node to which the first clock signal, the J th clock signal, or the N th clock signal is input;

a gate-on voltage node to which a gate-on voltage is applied; and

a gate-off voltage node to which a gate-off voltage is applied,

wherein each of the first clock signal and the J th clock signal swings between a gate-on voltage and a gate-off voltage, and

wherein, when the gate-on voltage of the J th clock signal differs from the gate-on voltage of the first clock signal, a compensation gate-on voltage at a changed voltage level is applied to the gate-on voltage node of the J th stage.

2. The gate driver of claim 1 , wherein the J th stage includes:

a first output node which outputs the J th gate signal including a scan signal and an emission control signal;

a second output node which outputs the J th carry signal;

a start node to which the J−1 th carry signal is input;

a first transistor that activates a QC node by applying any one of the compensation gate-on voltage or the gate-off voltage to the QC node according to the J th clock signal;

a sixth transistor that supplies the J th gate signal at the gate-on voltage to the first output node from when a first control node is bootstrapped in synchronization with an activated timing of the QC node;

a QB control unit configured to activate a QB node opposite to the QC node according to potentials of the clock node, the start node, and the QC node; and

a seventh transistor that supplies the J th gate signal at the gate-off voltage to the first output node while the QB node is activated before the QC node is activated,

wherein the compensation gate-on voltage is applied to the second output node.

3. The gate driver of claim 2 , further comprising:

an eighth transistor disposed between the gate-on voltage node and the second output node of the J th stage; and

a ninth transistor disposed between the gate-off voltage node and the second output node of the J th stage.

4. The gate driver of claim 3 , wherein the gate-on voltage received from a power supply unit is applied to the first output node of the J th stage.

5. The gate driver of claim 1 , wherein the J th stage includes:

an output node which outputs the J th gate signal including a scan signal and an emission control signal;

a start node to which the J−1 th carry signal is input;

a first transistor that activates a QC node by applying any one of the compensation gate-on voltage and the gate-off voltage to the QC node according to the J th clock signal;

a sixth transistor that supplies the J th gate signal at the gate-on voltage to the output node from when a first control node is bootstrapped in synchronization with an activated timing of the QC node;

a QB control unit configured to activate a QB node opposite to the QC node according to potentials of the clock node, the start node, and the QC node;

a seventh transistor that supplies the J th gate signal at the gate-off voltage to the output node while the QB node is activated before the QC node is activated; and

a tenth transistor that applies the compensation gate-on voltage to the first transistor according to the J−1 th carry signal,

wherein the gate-off voltage node includes a first gate-off voltage node to which a first gate-off voltage is applied, and a second gate-off voltage node to which a second gate-off voltage is applied.

6. The gate driver of claim 5 , further comprising an eleventh transistor that applies the second gate-off voltage to the first transistor according to a potential of the QB node of a J−1 th stage.

7. The gate driver of claim 5 , further comprising a thirteenth transistor that applies the second gate-off voltage to the first transistor according to the J−1 th carry signal.

8. The gate driver of claim 7 , wherein the thirteenth transistor applies the second gate-off voltage to the first transistor according to the J−1 th carry signal inverted.

9. The gate driver of claim 5 , wherein the QB control unit includes:

a fifth capacitor connected between an input terminal of the J th clock signal and a QD node;

a third transistor that supplies the J th clock signal to the QB node according to a potential of the QD node;

a second transistor that supplies a first gate-off voltage to the QD node according to the J−1 th carry signal; and

a fourth transistor that supplies the first gate-off voltage to the QB node according to the potential of the QC node.

10. The gate driver of claim 1 , wherein the gate-on voltage applied to the gate-on voltage node is a first constant voltage, and the gate-off voltage applied to the gate-off voltage node is a second constant voltage.

11. The gate driver of claim 10 , wherein the J th stage includes:

an output node which outputs the J th gate signal including a scan signal, an emission control signal, and the J th carry signal;

a start node to which the J−1 th carry signal is input;

a first transistor that activates a QC node by applying any one of the compensation gate-on voltage and the gate-off voltage to the QC node according to the J th clock signal;

a sixth transistor that supplies the J th gate signal at the gate-on voltage to the output node from when a first control node is bootstrapped in synchronization with an activated timing of the QC node;

a QB control unit configured to activate a QB node opposite to the QC node according to potentials of the clock node, the start node, and the QC node; and

a seventh transistor that supplies the J th gate signal at the gate-off voltage to the output node while the QB node is activated before the QC node is activated.

12. The gate driver of claim 11 , wherein, when the first control node is bootstrapped, a potential of the QC node differs from a potential of the first control node.

13. The gate driver of claim 12 , further comprising a fifth transistor that blocks electrical connection between the QC node and the first control node when the first control node is bootstrapped.

14. The gate driver of claim 13 , wherein a gate electrode of the fifth transistor is connected to the gate-on voltage node to which the first constant voltage is applied, a first electrode of the fifth transistor is connected to the QC node, and a second electrode of the fifth transistor is connected to the first control node.

15. The gate driver of claim 14 , wherein the QB control unit includes:

a fifth capacitor connected between an input terminal of the J th clock signal and a QD node;

a third transistor that supplies the J th clock signal to the QB node according to a potential of the QD node;

a second transistor that supplies a first gate-off voltage to the QD node according to the J−1 th carry signal; and

a fourth transistor that supplies the first gate-off voltage to the QB node according to a potential of the QC node.

16. The gate driver of claim 15 , wherein the potential of the QD node is changed in synchronization with the J th clock signal while the J−1 th carry signal is maintained at the gate-off voltage, and

wherein the potential of the QD node becomes the gate-off voltage while the J−1 th carry signal is maintained at the gate-on voltage.

17. The gate driver of claim 10 , wherein the first constant voltage is applied to the gate-on voltage nodes of the first stage to the N th stage through one line.

18. The gate driver of claim 1 , wherein the J th stage is an N th stage.

19. The gate driver of claim 1 , wherein, when the gate-on voltage of the J th clock signal is higher than the gate-on voltage of the first clock signal, a voltage level of the gate-on voltage applied to the gate-on voltage node increases.

20. A display device comprising;

a display panel on which a plurality of gate lines, a plurality of power lines, and the gate driver of claim 1 are disposed;

wherein the gate driver receives the first clock signal, the J th clock signal, or the N th clock signal from a clock generation circuit and supplies the first gate signal, the J th gate signal, or the N th gate signal swinging between the gate-on voltage and the gate-off voltage to the plurality of gate lines;

a power supply unit configured to generate power input to the display panel and the gate driver through the plurality of power lines;

a sensing unit configured to sense the first clock signal, the J th clock signal, or the N th clock signal input to the gate driver; and

a compensation unit configured to apply a compensation gate-on voltage to the gate driver based on the first clock signal, the J th clock signal, or the N th clock signal sensed by the sensing unit.

21. The display device of claim 20 , wherein the sensing unit senses the J th clock signal.

22. The display device of claim 21 , wherein the sensing unit senses the N th clock signal.

23. The display device of claim 21 , wherein the gate-on voltage of the J th clock signal sensed by the sensing unit differs from the gate-on voltage of the first clock signal.

24. A method of driving a display device including a plurality of stages cascade-connected to each other through a carry signal line, wherein the plurality of stages includes a first stage configured to receive a first clock signal and a start signal, and output a first gate signal and a first carry signal, a J th stage configured to receive a J th clock signal and a J−1 th carry signal, and output a J th gate signal and a J th carry signal, wherein J is a positive integer that is greater than or equal to 2 and less than or equal to N, and an N th stage configured to receive an N th clock signal and an N−1 th carry signal, and output an N th gate signal and an N th carry signal, wherein N is a natural number that is greater than or equal to 2, and each of the first stage, the J th stage, and the N th stage includes a clock node to which the first clock signal, the J th clock signal, or the N th clock signal is input, a gate-on voltage node to which a gate-on voltage is applied, and a gate-off voltage node to which a gate-off voltage is applied, the method comprising:

sensing the gate-on voltage of the J th clock signal input to the J th stage;

causing a difference between the gate-on voltage of the J th clock signal sensed by the sensing and the gate-on voltage of the first clock signal; and

applying a compensation gate-on voltage to the gate-on voltage node of the J th stage, wherein a voltage level of the compensation gate-on voltage is changed based on the gate-on voltage of the J th clock signal and the gate-on voltage of a clock signal input from a clock generation circuit.