Methods and apparatus to facilitate read-modify-write support in a victim cache
Methods, apparatus, systems and articles of manufacture are disclosed to facilitate read-modify-write support in a victim cache. An example apparatus includes a first storage coupled to a controller, a second storage coupled to the controller and parallel coupled to the first storage, and a storage queue coupled to the first storage, the second storage, and to the controller, the storage queue to obtain a memory operation from the controller indicating an address and a first set of data, obtain a second set of data associated with the address from at least one of the first storage and the second storage, merge the first set of data and the second set of data to produce a third set of data, and provide the third set of data for writing to at least one of the first storage and the second storage.
1 . A device, comprising:
a cache controller;
a first cache storage coupled to the cache controller;
a second cache storage coupled to the cache controller in parallel with the first cache storage; and
a storage queue coupled to the second cache storage and the cache controller,
wherein the cache controller is configured to cause the storage queue to:
receive a first set of data from the first cache storage;
receive a second set of data from the second cache storage;
merge the first set of data and the second set of data to produce a third set of data; and
write the third set of data to the second cache storage.
2 . The device of claim 1 , wherein the storage queue is configured to receive a memory operation that indicates an address and includes the first set of data.
3 . The device of claim 2 , wherein the second set of data is associated with the address.
4 . The device of claim 1 , wherein the storage queue comprises a read-modify-write circuit configured to merge the first set of data and the second set of data to produce the third set of data.
5 . The device of claim 1 , wherein:
the storage queue comprises an error correcting code generator circuit configured to generate a set of error correcting code syndrome bits based on the third set of data; and
the storage queue is configured to write the set of error correcting code syndrome bits to the second cache storage.
6 . The device of claim 1 , wherein
the first cache storage is a level one (L1) main cache storage; and
the second cache storage is an L1 victim cache storage.
7 . The device of claim 6 , further comprising:
a level two (L2) cache storage; and
an L2 interface configured to receive the third set of data for writing to the L2 cache storage.
8 . A system, comprising:
a processing unit configured to generate a memory operation;
a cache controller configured to receive the memory operation;
a first cache storage coupled to the cache controller;
a second cache storage coupled to the cache controller in parallel with the first cache storage; and
a storage queue coupled to the second cache storage and the cache controller,
wherein the cache controller is configured to cause, based on the memory operation, the storage queue to:
receive a first set of data from the first cache storage;
receive a second set of data from the second cache storage;
merge the first set of data and the second set of data to produce a third set of data; and
write the third set of data to the second cache storage.
9 . The system of claim 8 , wherein the memory operation indicates an address and includes the first set of data.
10 . The system of claim 9 , wherein the second set of data is associated with the address.
11 . The system of claim 8 , wherein the storage queue comprises a read-modify-write circuit configured to merge the first set of data and the second set of data to produce the third set of data.
12 . The system of claim 8 , wherein:
the storage queue comprises an error correcting code generator circuit configured to generate a set of error correcting code syndrome bits based on the third set of data; and
the storage queue is configured to write the set of error correcting code syndrome bits to the second cache storage.
13 . The system of claim 8 , wherein
the first cache storage is a level one (L1) main cache storage; and
the second cache storage is an L1 victim cache storage.
14 . The system of claim 13 , further comprising:
a level two (L2) cache storage; and
an L2 interface configured to receive the third set of data for writing to the L2 cache storage.
15 . A method, comprising:
retrieving, by a cache controller, a first set of data from a first cache storage;
providing the first set of data to a storage queue coupled to a second cache storage;
retrieving a second set of data from the second cache storage;
merging, by the storage queue, the first set of data and the second set of data to produce a third set of data; and
storing, by the storage queue, the third set of data in the second cache storage.
16 . The method of claim 15 , wherein the storage queue receives a memory operation that indicates an address and includes the first set of data.
17 . The method of claim 16 , wherein the second set of data is associated with the address.
18 . The method of claim 15 , further comprising:
generating a set of error correcting code syndrome bits based on the third set of data; and
storing the set of error correcting code syndrome bits in the second cache storage.
19 . The method of claim 15 , wherein:
the first cache storage is a level one (L1) main cache storage; and
the second cache storage is an L1 victim cache storage.
20 . The method of claim 19 , further comprising:
providing the third set of data to a level two (L2) cache storage for writing.