IP Library › Granted Patent US 12,647,204
Granted Patent B2
US 12,647,204 · App. 18/775,927 · Granted Jun 2, 2026

Method, apparatus, and system for improving reliability of data transmission involving an ethernet device

Inventors: Yuchun Lu (Beijing, CN); Yan Zhuang (Nanjing, CN)
Assignee: Huawei Technologies Co., Ltd.
H04L1/0042H04L1/0003
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Quick Facts
Patent No.
US 12,647,204
App. No.
18/775,927
Granted
Jun 2, 2026
Kind
B2
Abstract

A data transmission method, apparatus, and system are applied to the field of communication technologies. The method includes: performing demultiplexing processing on obtained y first data streams to obtain x second data streams, where the y first data streams are obtained through bit multiplexing processing; mapping the x second data streams at a granularity of n bits to obtain z third data streams; and outputting the z third data streams over an output lane, where y, x, n, and z are all positive integers, and n≥2. The method may be applied to an Ethernet high-speed interface.

Claims (54)

1 . A data transmission method, comprising:

performing, by a physical medium attachment (PMA) layer of a physical layer (PHY) chip of a transmitting device, processing on at least one of x second data streams to obtain x processed second data streams, wherein the processing includes modification of a timing of the at least one of the x second data streams, where x is a positive integer;

performing, by the PMA layer, first block-level multiplexing processing on the x processed second data streams to obtain z third data stream(s), where z is a positive integer, x>z, and z≥1; and

outputting, by the PMA layer, the z third data stream(s) over z output lane(s).

2 . The method according to claim 1 , further comprising:

performing, by the PMA layer, bit-level demultiplexing processing on y first data streams to obtain y demultiplexed first data streams, wherein the y first data streams are based on bit-level multiplexing processing, where y is a positive integer, and x>y.

3 . The method according to claim 2 , further comprising:

performing, by the PMA layer, second block-level multiplexing processing on the y demultiplexed first data streams to obtain the x second data streams.

4 . The method according to claim 3 , wherein in each pair of adjacent second data streams of the x second data streams, symbols located at a same position in the second data streams of the respective pair comprise a symbol from first forward error correction (FEC) encoded data and a symbol from second FEC encoded data.

5 . The method according to claim 4 , wherein each pair of adjacent symbols in each data stream of the x second data streams includes a symbol from the first FEC encoded data and a symbol from the second FEC encoded data.

6 . The method according to claim 1 , wherein performing first block-level multiplexing processing on the x processed second data streams to obtain the z third data stream(s) comprises:

performing the first block-level multiplexing processing on the x processed second data streams in a round-robin fashion to obtain the z third data stream(s).

7 . The method according to claim 6 , wherein z=1, and wherein performing the first block-level multiplexing processing on the x processed second data streams in the round-robin fashion to obtain the third data stream comprises:

sequentially multiplexing data of n consecutive bits obtained from each of the x processed second data streams according to a round robin sequence for the x processed second data streams, to obtain the third data stream, wherein n≥2.

8 . The method according to claim 6 , wherein z≥2, x≥3, and wherein performing the first block-level multiplexing processing on the x processed second data streams in the round-robin fashion to obtain the z third data streams comprises:

sequentially multiplexing data of n consecutive bits obtained from each of the x processed second data streams to respective third data streams according to a round robin sequence for the x processed second data streams and the z third data streams until all data of the x processed second data streams is mapped to obtain the z third data streams, wherein n≥2.

9 . The method according to claim 1 , wherein the modification of the timing of the at least one of the x second data streams comprises alignment processing or deskew processing.

10 . A data transmission method, comprising:

obtaining, by a physical medium attachment (PMA) layer of a physical layer (PHY) chip of a receiving device, z third data stream(s) over z input lane(s), wherein the z third data stream(s) are based on first block-level multiplexing processing, where z is a positive integer, and z≥1;

performing, by the PMA layer, first block-level demultiplexing processing on the z third data stream(s) to obtain x demultiplexed second data streams, where x is a positive integer, and x>z; and

performing, by the PMA layer, processing on at least one of x demultiplexed second data streams to obtain x processed second data streams, wherein the processing includes modification of a timing of the at least one of the x demultiplexed second data streams.

11 . The method according to claim 10 , further comprising:

outputting, by the PMA layer, the x second data streams, wherein the x second data streams are obtained by performing second block-level multiplexing processing on first forward error correction (FEC) encoded data and second FEC encoded data.

12 . The method according to claim 11 , wherein each pair of adjacent symbols in each data stream of the x second data streams includes a symbol from the first FEC encoded data and a symbol from the second FEC encoded data.

13 . The method according to claim 10 , wherein the receiving device is an ethernet device.

14 . The method according to claim 1 , wherein the modification of the timing of the at least one of the x demultiplexed second data streams comprises alignment processing or deskew processing.

15 . A transmitting device, comprising:

a physical medium attachment (PMA) layer of a physical layer (PHY) chip, wherein the PMA layer is configured to:

perform processing on at least one of x second data streams to obtain x processed second data streams, wherein the processing includes modification of a timing of the at least one of the x second data streams, where x is a positive integer;

perform first block-level multiplexing processing on the x processed second data streams to obtain z third data stream(s), where z is a positive integer, x>z, and z≥1; and

an interface configured to output the z third data stream(s) over z output lane(s).

16 . The transmitting device according to claim 15 , wherein the PMA layer is further configured to:

perform bit-level demultiplexing processing on y first data streams to obtain y demultiplexed first data streams, wherein the y first data streams are based on bit-level multiplexing processing, where y is a positive integer, and x>y.

17 . The transmitting device according to claim 16 , wherein the PMA layer is further configured to:

perform second block-level multiplexing processing on the y demultiplexed first data streams to obtain the x second data streams.

18 . The transmitting device according to claim 17 , wherein in each pair of adjacent second data streams of the x second data streams, symbols located at a same position in the second data streams of the respective pair comprise a symbol from first forward error correction (FEC) encoded data and a symbol from second FEC encoded data.

19 . The transmitting device according to claim 18 , wherein each pair of adjacent symbols in each data stream of the x second data streams includes a symbol from the first FEC encoded data and a symbol from the second FEC encoded data.

20 . The transmitting device according to claim 15 , wherein the PMA layer is configured to:

perform the first block-level multiplexing processing on the x processed second data streams in a round-robin fashion to obtain the z third data stream(s).

21 . The transmitting device according to claim 20 , wherein z=1, and the PMA layer is configured to:

sequentially multiplex data of n consecutive bits obtained from each of the x processed second data streams according to a round robin sequence for the x processed second data streams, to obtain the third data stream, wherein n≥2.

22 . The transmitting device according to claim 20 , wherein z≥2, x≥3, and the PMA layer is configured to:

sequentially multiplex data of n consecutive bits obtained from each of the x processed second data streams to respective third data streams according to a round robin sequence for the x processed second data streams and the z third data streams until all data of the x processed second data streams is mapped to obtain the z third data streams, wherein n≥2.

23 . The transmitting device according to claim 15 , wherein the modification of the timing of the at least one of the x second data streams comprises alignment processing or deskew processing.

24 . A receiving device, comprising:

a first interface configured to obtain z third data stream(s) over z input lane(s), wherein the z third data stream(s) are based on first block-level multiplexing processing, where z is a positive integer, and z≥1; and

a physical medium attachment (PMA) layer of a physical layer (PHY) chip, wherein the PMA layer is configured to:

perform first block-level demultiplexing processing on the z third data stream(s) to obtain x demultiplexed second data streams, where x is a positive integer, and x>z; and

perform processing on at least one of x demultiplexed second data streams to obtain x processed second data streams, wherein the processing includes modification of a timing of the at least one of the x demultiplexed second data streams.

25 . The receiving device according to claim 24 , wherein the receiving device further comprises:

a second interface configured to output the x second data streams, wherein the x second data streams are obtained by performing second block-level multiplexing processing on first forward error correction (FEC) encoded data and second FEC encoded data.

26 . The receiving device according to claim 25 , wherein each pair of adjacent symbols in each data stream of the x second data streams includes a symbol from the first FEC encoded data and a symbol from the second FEC encoded data.

27 . The receiving device according to claim 24 , wherein the receiving device is an ethernet device.

28 . The receiving device according to claim 24 , wherein the modification of the timing of the at least one of the x demultiplexed second data streams comprises alignment processing or deskew processing.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 22, 2025
From: BEIJING HUAWEI DIGITAL TECHNOLOGIES CO., LTD.
To: HUAWEI TECHNOLOGIES CO., LTD.
Reel/Frame 072100/0480 →
EMPLOYEE AGREEMENT Recorded Aug 22, 2025
From: LU, YUCHUN
To: BEIJING HUAWEI DIGITAL TECHNOLOGIES CO., LTD.
Reel/Frame 072527/0903 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 17, 2024
From: LU, YUCHUN; ZHUANG, YAN
To: HUAWEI TECHNOLOGIES CO., LTD.
Reel/Frame 068014/0046 →
Priority Claims (1)
CN 201910169228.6 · Mar 6, 2019 · national
Continuity (4)
Continuation 18427263 · Jan 30, 2024
Continuation 17466903 · Sep 3, 2021
Continuation PCTCN2020076806 · Feb 26, 2020
Related Publication 20250007647A1 · Jan 2, 2025
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