IP Library › Granted Patent US 12,748,692
Granted Patent B2
US 12,748,692 · App. 18/781,982 · Granted Sep 29, 2026

Address translation in a memory sub-system for memory pooling

Inventor: Rishabh Dubey (Agrate Brianza, IT)
Assignee: Micron Technology, Inc.
G06F12/0246G06F12/0284G06F12/0292G06F12/1072
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Quick Facts
Patent No.
US 12,748,692
App. No.
18/781,982
Granted
Sep 29, 2026
Kind
B2
Abstract

A system including a memory device and an operatively coupled processing device to perform operations determining a size of a minimum allocation unit (MAU) for a plurality of logical devices, dividing the memory device into logical units with a size equal to the MAU, identifying, using a logical device identifier (LDI) data structure, a first LDI that is available, wherein the first LDI identifies a first logical device, identifying, using a logical unit identifier (LUI) data structure, a first set of LUI that are available, wherein the first set of LUI identify a first set of logical units, allocating the first set of logical units to the first logical device, and updating an LDI-to-LUI mapping data structure to reflect that the first set of logical units are allocated to the first logical device.

Claims (63)

1 . A method comprising:

determining, for a plurality of logical devices, a minimum allocation unit (MAU) size comprising a minimum quantity of data usable by a logical device of the plurality of logical devices;

dividing the memory device into a plurality of logical units using the MAU size as a reference, wherein each logical unit has a size equal to the MAU size;

identifying, using a logical device identifier (LDI) data structure, a first LDI that is available, wherein the first LDI identifies a first logical device of the plurality of logical devices;

attempting to identify, using a logical unit identifier (LUI) data structure, a first set of LUIs that are available and consecutive, wherein the first set of LUIs identifies a first set of logical units of the plurality of logical units;

responsive to failing to identify the consecutive set of LUIs from the first set of LUIs that are available, assigning available nonconsecutive LUIs to the first set of LUIs;

allocating the first set of logical units to the first logical device; and

updating an LDI-to-LUI mapping data structure to reflect allocation of the first set of logical units are allocated to the first logical device.

2 . The method of claim 1 , wherein updating the LDI-to-LUI mapping data structure further comprises:

updating the LDI data structure to reflect that the first LDI is unavailable; and

updating the LUI data structure to reflect that each LUI of the first set of LUIs is unavailable.

3 . The method of claim 1 , wherein the first set of LUIs comprises a subset of consecutive LUIs.

4 . The method of claim 1 , wherein each logical unit of the plurality of logical units is associated with a respective set of consecutive physical addresses of a plurality of physical addresses comprised by a physical address space associated with the memory device.

5 . The method of claim 4 , wherein a first logical address space associated with the first logical device maps to physical addresses associated with the first set of logical units.

6 . The method of claim 5 , comprising:

translating, using the LDI-to-LUI mapping data structure, a first logical address of the first logical device to a first physical address of the plurality of physical addresses of the memory device.

7 . The method of claim 1 , comprising:

deallocating the first set of logical units from the first logical device; and

updating the LDI-to-LUI mapping data structure to reflect that the first set of logical units are not allocated to the first logical device.

8 . The method of claim 1 , comprising:

identifying, using the LDI data structure, a second LDI that is available, wherein the second LDI identifies a second logical device of the plurality of logical devices;

identifying, using the LUI data structure, a second set of LUIs that are available, wherein the second set of LUIs identify a second set of logical units of the plurality of logical units;

allocating the second set of logical units to the second logical device; and

updating the LDI-to-LUI mapping data structure to reflect allocation of the second set of logical units to the second logical device.

9 . The method of claim 1 , comprising:

receiving a request to allocate logical units of the plurality of logical units to a logical device of the plurality of logical devices.

10 . A computer-readable non-transitory storage medium comprising executable instructions that, when executed by a controller managing a memory device comprising a plurality of memory cells, cause the controller to:

determine, for a plurality of logical devices, a size of a minimum allocation unit (MAU) comprising a minimum quantity of data usable by a logical device of the plurality of logical devices;

divide the memory device into a plurality of logical units using the MAU size as a reference, wherein each logical unit has a size equal to the MAU;

identify, using a logical device identifier (LDI) data structure, a first LDI that is available, wherein the first LDI identifies a first logical device of the plurality of logical devices;

attempt to identify, using a logical unit identifier (LUI) data structure, a first set of LUIs that are available and consecutive, wherein the first set of LUIs identifies a first set of logical units of the plurality of logical units;

responsive to failing to identify the consecutive set of LUIs from the first set of LUIs that are available, assign available nonconsecutive LUIs to the first set of LUIs;

allocate the first set of logical units to the first logical device; and

update an LDI-to-LUI mapping data structure to reflect that the first set of logical units are allocated to the first logical device.

11 . The computer-readable non-transitory storage medium of claim 10 , wherein each logical unit of the plurality of logical units is associated with a respective set of consecutive physical addresses of a plurality of physical addresses comprised by a physical address space associated with the memory device.

12 . A system comprising:

a memory device; and

a processing device, operatively coupled with the memory device, to perform operations comprising:

determining, for a plurality of logical devices, a minimum allocation unit (MAU) size corresponding to a minimum quantity of data usable by a logical device of the plurality of logical devices;

dividing the memory device into a plurality of logical units using the MAU size as a reference, wherein each logical unit has a size equal to the MAU size;

identifying, using a logical device identifier (LDI) data structure, a first LDI that is available, wherein the first LDI identifies a first logical device of the plurality of logical devices;

attempting to identify, using a logical unit identifier (LUI) data structure, a first set of LUIs that are available and consecutive, wherein the first set of LUIs identifies a first set of logical units of the plurality of logical units;

responsive to failing to identify the consecutive set of LUIs from the first set of LUIs that are available, assigning available nonconsecutive LUIs to the first set of LUIs;

allocating the first set of logical units to the first logical device; and

updating an LDI-to-LUI mapping data structure to reflect allocation of the first set of logical units to the first logical device.

13 . The system of claim 1 , wherein updating the LDI-to-LUI mapping data structure further comprises:

updating the LDI data structure to reflect that the first LDI is unavailable; and

updating the LUI data structure to reflect that each LUI of the first set of LUIs is unavailable.

14 . The system of claim 1 , wherein the first set of LUIs comprises a subset of consecutive LUIs.

15 . The system of claim 12 , wherein each logical unit of the plurality of logical units is associated with a respective set of consecutive physical addresses of a plurality of physical addresses comprised by a physical address space associated with the memory device.

16 . The system of claim 15 , wherein a first logical address space associated with the first logical device maps to physical addresses associated with the first set of logical units.

17 . The system of claim 16 , the operations further comprising:

translating, using the LDI-to-LUI mapping data structure, a first logical address of the first logical device to a first physical address of the plurality of physical addresses of the memory device.

18 . The system of claim 12 , the operations further comprising:

deallocating the first set of logical units from the first logical device; and

updating the LDI-to-LUI mapping data structure to reflect that the first set of logical units are not allocated to the first logical device.

19 . The system of claim 1 , the operations further comprising:

identifying, using the LDI data structure, a second LDI that is available, wherein the second LDI identifies a second logical device of the plurality of logical devices;

identifying, using the LUI data structure, a second set of LUIs that are available, wherein the second set of LUIs identify a second set of logical units of the plurality of logical units;

allocating the second set of logical units to the second logical device; and

updating the LDI-to-LUI mapping data structure to reflect allocation of the second set of logical units to the second logical device.

20 . The system of claim 12 , the operations further comprising:

receiving a request to allocate logical units of the plurality of logical units to a logical device of the plurality of logical devices.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 25, 2025
From: DUBEY, RISHABH
To: MICRON TECHNOLOGY, INC.
Reel/Frame 070618/0102 →
Continuity (2)
Provisional Application 63591400 · Oct 18, 2023
Related Publication 20250130937A1 · Apr 24, 2025
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