Ultra-low power instant lock phase lock loop (PLL)
Systems and methods reduce a locking time of a type-II all-digital phase-locked loop (ADPLL) circuit by performing steps that comprise receiving a reference signal having a reference frequency and setting a digitally controlled oscillator (DCO) to a target frequency greater than the reference frequency. The DCO generates an output signal that is used to generate a feedback signal. A time-to-digital converter is used to determine an initial phase difference between the reference signal and the feedback signal, and a digital initial phase compensation circuit adjusts the initial phase difference to a substantially zero phase difference to reduce the locking time of the ADPLL circuit such that the ADPLL circuit reaches a steady-state condition in ten or fewer cycles of the reference signal.
1 . A method to reduce a locking time of a phase-locked loop (PLL), the method comprising:
setting a digitally controlled oscillator (DCO) in the PLL to a desired frequency;
generating, in a feedback path of the PLL, a feedback signal from an output of the DCO;
detecting, at a time-to-digital converter (TDC) in the PLL, an initial phase difference between the feedback signal and a reference signal;
encoding, by a digital phase compensation circuit in the PLL, the initial phase difference as an offset such that the initial phase difference is treated as a zero phase difference; and
providing the zero phase difference as an initial condition to a digital loop filter (DLP) in the PLL for PLL locking.
2 . The method of claim 1 , wherein the offset is locked in a next clock cycle of the reference signal.
3 . The method of claim 1 , wherein the desired frequency is calibrated in an open loop configuration to determine a digital code.
4 . The method of claim 3 , wherein the digital code is generated by a frequency encoder that effectuates a desired lock frequency for a closed loop of the PLL within a predetermined accuracy range.
5 . The method of claim 1 , wherein the desired frequency is calibrated during a power-up phrase of the PLL.
6 . The method of claim 1 , wherein the initial phase difference is a relative time difference in rising edges of the feedback signal and the reference signal.
7 . The method of claim 1 , wherein the feedback path comprises a frequency divider.
8 . The method of claim 1 , wherein the DLP is a low-pass filter that attenuates high-frequency and phase noise contained in an output of the TDC.
9 . The method of claim 8 , wherein the output of the TDC is a non-negative error signal that represents a phase difference between input signals of the TDC.
10 . The method of claim 1 , wherein the DCO is a variable phase device that uses a free-running crystal oscillator to generate a variable clock signal.
11 . A phase-locked loop (PLL) circuit comprising:
a digitally controlled oscillator (DCO) that is initially set to a desired frequency;
a feedback path to provide a feedback signal from an output of the DCO;
a time-to-digital converter (TDC) that detects an initial phase difference between the feedback signal and a reference signal;
a digital phase compensation circuit that encodes the initial phase difference as an offset to zero out the initial phase difference as a zero phase difference; and
a digital loop filter (DLP) that receives the zero phase difference as an initial condition to for PLL locking.
12 . The PLL of claim 11 , wherein the offset is locked in a next clock cycle of the reference signal.
13 . The PLL of claim 11 , wherein the desired frequency is calibrated in an open loop configuration to determine a digital code.
14 . The PLL of claim 13 , wherein the digital code is generated by a frequency encoder that effectuates a desired lock frequency for a closed loop of the PLL within a predetermined accuracy range.
15 . The PLL of claim 11 , wherein the desired frequency is calibrated during a power-up phrase of the PLL.
16 . The PLL of claim 11 , wherein the initial phase difference is a relative time difference in rising edges of the feedback signal and the reference signal.
17 . The PLL of claim 11 , wherein the feedback path comprises a frequency divider.
18 . The PLL of claim 11 , wherein the DLP is a low-pass filter that attenuates high-frequency and phase noise contained in an output of the TDC.
19 . The PLL of claim 18 , wherein the output of the TDC is a non-negative error signal that represents a phase difference between input signals of the TDC.
20 . The PLL of claim 11 , wherein the DCO is a variable phase device that uses a free-running crystal oscillator to generate a variable clock signal.